2024-11-28 06:47:26 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.74.20:5700'
2024-11-28 06:47:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.74.20:5802)
2024-11-28 06:47:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.74.20:5801)
2024-11-28 06:47:26 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.74.22:6700'
2024-11-28 06:47:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.74.22:6802)
2024-11-28 06:47:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.74.22:6801)
2024-11-28 06:47:26 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.74.20:5700/1'
2024-11-28 06:47:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.74.20:5804)
2024-11-28 06:47:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.74.20:5803)
2024-11-28 06:47:26 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.74.20:5700/2'
2024-11-28 06:47:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.74.20:5806)
2024-11-28 06:47:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.74.20:5805)
2024-11-28 06:47:26 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.74.20:5700/3'
2024-11-28 06:47:26 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.74.20:5808)
2024-11-28 06:47:26 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.74.20:5807)
2024-11-28 06:47:26 [INFO] fake_trx.py:423 Init complete
2024-11-28 06:47:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 0 -> 1
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 0 -> 1
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 0 -> 1
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 0 -> 1
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:47:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:47:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:47:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:47:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:47:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2752 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2752 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2752 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2753 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:47:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:47:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:47:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:47:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 06:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 06:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2024-11-28 06:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
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2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:47:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:47:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:47:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:47:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:47:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:47:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:47:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:48:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:48:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:48:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:48:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:48:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:48:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:48:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:48:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:48:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:48:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:48:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:48:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:48:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:48:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:48:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:48:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:48:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:48:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:48:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:48:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 06:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 06:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 06:48:43 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 06:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 06:48:44 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 06:48:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 06:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 06:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 06:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 06:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 06:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 06:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 06:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 06:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 06:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 06:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 06:48:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 06:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 06:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 06:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 06:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 06:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 06:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 06:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 06:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 06:48:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 06:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 06:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 06:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 06:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 06:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 06:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 06:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:48:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:48:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 06:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 06:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 06:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 06:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 06:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 06:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 06:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 06:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 06:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 06:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 06:49:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 06:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 06:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 06:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 06:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 06:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 06:49:07 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 06:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 06:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 06:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 06:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 06:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 06:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 06:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 06:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 06:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 06:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 06:49:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 06:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 06:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 06:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 06:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 06:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 06:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 06:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 06:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 06:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 06:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 06:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 06:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 06:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 06:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 06:49:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 06:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 06:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 06:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 06:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 06:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 06:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 06:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 06:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 06:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 06:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 06:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 06:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 06:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 06:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 06:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 06:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 06:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 06:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 06:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 06:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 06:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 06:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 06:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 06:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 06:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 06:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 06:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 06:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 06:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 06:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 06:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 06:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 06:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 06:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 06:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 06:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 06:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 06:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:49:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:49:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:49:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19535 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:49:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:49:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:49:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:49:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:49:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:49:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:49:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:49:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:49:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:49:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:49:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:49:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:49:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:49:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:49:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:49:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:49:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:49:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:49:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:49:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:50:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:50:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:50:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:50:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:50:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:50:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:50:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:50:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:50:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:50:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:08 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:50:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:50:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:50:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:50:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:50:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:50:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:50:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:50:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:50:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:50:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:50:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:50:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:50:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:50:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:50:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:50:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:50:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:50:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 06:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 06:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 06:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 06:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 06:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 06:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 06:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 06:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 06:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 06:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 06:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 06:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 06:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 06:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 06:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 06:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 06:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 06:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 06:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 06:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 06:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 06:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 06:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 06:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 06:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 06:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 06:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 06:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 06:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 06:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 06:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 06:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 06:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 06:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 06:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 06:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 06:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 06:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 06:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 06:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 06:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 06:51:32 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 06:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 06:51:33 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 06:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 06:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 06:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 06:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 06:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 06:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 06:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 06:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 06:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 06:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 06:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 06:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 06:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 06:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 06:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 06:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 06:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 06:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 06:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 06:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 06:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 06:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 06:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 06:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 06:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 06:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 06:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 06:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 06:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 06:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 06:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 06:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 06:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 06:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 06:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 06:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 06:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 06:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 06:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 06:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 06:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 06:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 06:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 06:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 06:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 06:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 06:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 06:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:51:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:51:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 06:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 06:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 06:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 06:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 06:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 06:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 06:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 06:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 06:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 06:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 06:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 06:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 06:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 06:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:52:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:52:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:52:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:52:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:52:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:52:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:52:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:52:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:52:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:52:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:52:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:52:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:52:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:52:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:52:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:52:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:52:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:52:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:52:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:52:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:52:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:52:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:52:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:52:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:52:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:52:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:52:31 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:52:35 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 06:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 06:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 06:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 06:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 06:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 06:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 06:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 06:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 06:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 06:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 06:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 06:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 06:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 06:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 06:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 06:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 06:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 06:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 06:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 06:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 06:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 06:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 06:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 06:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:52:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:52:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 06:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 06:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 06:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 06:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 06:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 06:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 06:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 06:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 06:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 06:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 06:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 06:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 06:53:05 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 06:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 06:53:06 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 06:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 06:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 06:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 06:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 06:53:09 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 06:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 06:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 06:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 06:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 06:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 06:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 06:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 06:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 06:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 06:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 06:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 06:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 06:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 06:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 06:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 06:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 06:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 06:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 06:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 06:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 06:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 06:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 06:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 06:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 06:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 06:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 06:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 06:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 06:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 06:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 06:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 06:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 06:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 06:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 06:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 06:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 06:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 06:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 06:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 06:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 06:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 06:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 06:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 06:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 06:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 06:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 06:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 06:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:34 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 06:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 06:53:35 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 06:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 06:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 06:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 06:53:37 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 06:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 06:53:38 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 06:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 06:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 06:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 06:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 06:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 06:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 06:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 06:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 06:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 06:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 06:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 06:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 06:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 06:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 06:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 06:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:53:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:53:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:47 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:53:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:53:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:53:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:53:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:53:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:53:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:53:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:53:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:53:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:53:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:53:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:53:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:53:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:53:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:53:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:53:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:53:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:53:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:19 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:20 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:54:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:54:22 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:54:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:54:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:54:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:54:27 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:54:27 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:54:27 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:54:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:54:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:54:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:54:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:54:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:54:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:54:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:54:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:54:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:54:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:54:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:54:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:54:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:55:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:55:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:55:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:55:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:55:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:55:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:55:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:55:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:55:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:55:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:55:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 06:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 06:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 06:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 06:55:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 06:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 06:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 06:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 06:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 06:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 06:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 06:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 06:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 06:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 06:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 06:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 06:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 06:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 06:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 06:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 06:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 06:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 06:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 06:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 06:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 06:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 06:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 06:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 06:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 06:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 06:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 06:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 06:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 06:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 06:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 06:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 06:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 06:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 06:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 06:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 06:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 06:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 06:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 06:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 06:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 06:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 06:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 06:55:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 06:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 06:55:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:55:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:55:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:55:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:55:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:55:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:55:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:55:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:55:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:55:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:55:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:55:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:56:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:56:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:56:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:56:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:56:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:56:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:56:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:56:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:56:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:56:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:56:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:56:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:56:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:56:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:56:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:56:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:56:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:56:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:56:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:56:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:22 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:56:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:56:27 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:56:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:56:28 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:56:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:56:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:56:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:56:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:56:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2898 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:56:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:56:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:56:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:56:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:56:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:56:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:56:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:56:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:56:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:56:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:56:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:56:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:56:52 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:56:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:56:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:56:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:56:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:56:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:57:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:57:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=655 tn=4 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:57:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:57:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:57:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:57:22 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:57:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:22 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:57:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:57:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:57:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1308 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1308 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:57:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1308 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:57:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1308 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:33 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:57:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:57:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:57:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:57:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:57:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:44 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:57:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:57:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:57:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:57:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:57:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:57:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:57:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:57:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:57:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:57:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:57:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3317 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:58:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:58:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:58:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:58:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:58:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:58:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:58:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:58:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:58:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:58:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:58:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:58:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:58:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:58:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:58:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:58:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:58:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:58:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:58:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:58:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:58:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:58:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:58:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:58:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:58:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:58:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:58:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:45 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:58:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:58:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:58:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:58:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:58:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:59:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:59:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:59:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:59:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:59:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:59:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:59:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:59:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:59:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:59:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:59:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:59:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:59:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:59:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:59:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:59:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:59:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:59:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:59:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 06:59:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:59:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:59:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:59:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:59:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 06:59:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 06:59:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 06:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 06:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 06:59:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 06:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 06:59:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 06:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 06:59:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 06:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 06:59:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 06:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 06:59:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 06:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 06:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 06:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 06:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 06:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 06:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 06:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 06:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 06:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 06:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 06:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 06:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 06:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 06:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 06:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 06:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 06:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 06:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 06:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 06:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 06:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 06:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 06:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 06:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 06:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 06:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 06:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 06:59:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 06:59:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 06:59:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 06:59:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 06:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 06:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 06:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:00:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:00:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:00:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:00:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:00:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:00:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:00:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:00:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:00:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:00:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:00:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:00:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:00:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:00:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:00:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:00:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:00:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:00:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:00:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:00:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:00:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:00:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:00:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:00:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:00:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:01:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:01:13 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:01:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7108 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:01:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:01:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:01:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:01:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:01:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:01:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:01:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:01:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:01:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:01:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:01:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:01:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:01:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:01:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:01:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:01:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:01:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:01:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:01:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:01:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:01:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:01:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:01:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:01:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:27 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:01:47 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:01:47 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:01:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:01:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:01:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:01:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:01:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:02:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:02:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:02:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:02:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 07:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 07:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 07:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 07:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 07:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 07:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 07:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 07:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 07:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 07:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 07:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 07:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:02:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:02:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:02:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:02:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:02:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:02:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:02:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:02:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:02:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:02:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:02:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:02:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:02:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:02:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3619 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:02:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:02:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:02:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:02:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:02:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:02:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:02:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:02:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:02:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:02:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:02:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:02:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:02:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:02:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:02:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:02:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:02:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:03:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:03:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:03:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:03:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:03:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:03:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:03:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:03:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:03:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:03:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:03:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:03:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:03:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:03:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:03:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:03:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:03:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:03:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:03:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:03:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:03:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:03:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:03:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:03:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:03:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:03:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:03:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:03:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:03:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:03:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:03:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:03:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:03:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:03:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:03:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:03:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:03:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:03:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:03:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:03:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:03:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:03:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:03:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:03:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:03:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:03:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:03:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:04:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:04:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:04:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:04:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:04:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:06 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:04:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:04:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:08 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:04:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:04:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:09 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:04:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:04:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:04:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:04:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:04:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:04:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:04:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=126 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=127 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=128 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:16 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=217 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=218 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=219 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=220 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:04:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:04:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:04:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:04:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:04:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:04:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:04:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=126 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=127 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=128 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=130 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=131 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=133 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=134 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=136 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=137 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=139 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=140 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=143 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=145 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=146 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=148 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=149 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=151 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=152 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=154 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=157 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=158 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=160 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=161 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=163 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=164 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=166 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=167 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=169 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=170 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=172 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=173 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=175 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=176 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=178 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=179 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=182 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=184 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=185 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=187 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=188 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=190 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=191 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=193 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=196 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=197 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=199 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=200 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=202 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=203 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=205 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=206 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=208 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=209 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=211 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=212 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:23 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=214 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=215 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=217 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=218 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=219 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:04:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:04:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:04:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:04:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:04:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:04:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:04:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:04:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:04:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:04:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:04:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:04:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:04:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:05:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:05:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:05:12 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:05:13 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:05:14 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:05:15 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:05:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:05:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:16 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:05:16 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:05:26 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:05:27 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:05:28 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 07:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 07:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 07:05:29 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 07:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 07:05:30 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13456 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=13457 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:05:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:05:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:05:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:05:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:05:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:05:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:05:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:05:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:05:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:05:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:05:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:05:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:05:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:05:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:05:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:05:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:05:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:05:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:05:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:05:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:05:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:06:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:06:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:06:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:06:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:06:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:06:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:06:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:06:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:06:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:06:14 [DEBUG] fake_trx.py:263 (MS@172.18.74.22:6700) Recv SETTA cmd
2024-11-28 07:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:06:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:06:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:06:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:06:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:06:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:06:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:06:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:06:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:06:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:06:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:06:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:06:32 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:06:33 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:06:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:06:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:06:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:06:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:06:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:06:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:06:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:06:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:06:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:06:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:06:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:06:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:06:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:06:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:06:49 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2383 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:06:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:06:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:06:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:06:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:06:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:06:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:06:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:06:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:06:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:06:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:06:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:06:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:06:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:06:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:06:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:07:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:07:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:07:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:07:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:07:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:07:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:07:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:07:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:07:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:07:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:07:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:07:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:07:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:07:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:07:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:07:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:07:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:07:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:07:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:07:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:07:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:07:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:07:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:07:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:07:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:07:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:07:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:07:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:07:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:07:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2883 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:07:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:07:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:07:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:07:54 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:07:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:07:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:07:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:07:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:07:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:07:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:07:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:07:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:07:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:07:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:07:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:08:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:08:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:08:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:08:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:08:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:08:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:08:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:08:14 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:08:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:08:14 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:08:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:08:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:16 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=560 tn=6 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:16 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=560 tn=7 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:08:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:08:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:08:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:08:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:08:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:08:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:08:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:08:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:08:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:08:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:08:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:08:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:08:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:08:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:08:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:08:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:08:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:08:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:08:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:08:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:08:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:08:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:08:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:08:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:08:57 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:08:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:08:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:08:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:08:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:09:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:09:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:09:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:09:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:09:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:09:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:09:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:09:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:09:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:09:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:09:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:09:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:09:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:09:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:09:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:09:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:09:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:09:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:09:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:09:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:09:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:09:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:09:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:09:23 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:09:24 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:09:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:09:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:09:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:09:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:09:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:09:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:09:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:09:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:09:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:09:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:09:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:09:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:09:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:09:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:09:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:09:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:09:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:09:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:09:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:09:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:09:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:09:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:09:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:09:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:09:49 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:09:50 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:09:51 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:09:52 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:09:52 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:10:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:10:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:10:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:10:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:10:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:10:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:10:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:10:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:10:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:10:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:10:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:10:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:10:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:10:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:10:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:10:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:10:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:10:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:10:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:10:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:10:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:10:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:10:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:10:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:10:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:10:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:10:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:10:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:10:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:10:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:10:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:10:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:10:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:10:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:10:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:10:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:10:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:10:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:10:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:10:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:11:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:11:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:11:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:11:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:11:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:11:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:11:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:11:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:11:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:11:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:11:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:11:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:11:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:11:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:11:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:11:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:11:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:11:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:11:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:11:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:11:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:11:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:11:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:11:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:11:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:11:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:11:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:11:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:11:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:11:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:11:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:11:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:11:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:11:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:11:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:11:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:11:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:11:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:11:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:11:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:11:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:11:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:11:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:11:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:11:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:11:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:11:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:11:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:11:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:11:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:11:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:11:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:11:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:11:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:11:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:11:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:12:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:12:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:12:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:12:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:12:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:12:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:12:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:12:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:12:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:12:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:12:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:12:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:12:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:12:15 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:12:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:12:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:12:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:12:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:12:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:12:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:12:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:12:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:12:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:12:28 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:12:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:12:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:12:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:12:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:12:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:12:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:12:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:37 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:12:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:12:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:12:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:12:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:12:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:12:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:12:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:12:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:12:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:12:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:12:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:12:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:12:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:12:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:12:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:12:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:12:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:12:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:12:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:12:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:12:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:13:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:13:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:13:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:13:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:13:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:13:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:13:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:13:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:13:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:13:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:13:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:13:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:13:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:13:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:13:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:13:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:13:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:13:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:13:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:14:08 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:14:09 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:14:10 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:14:11 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:14:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:14:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:14:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:14:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:14:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:14:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:14:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:14:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:14:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:14:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=774 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:14:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=774 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:14:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:14:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:14:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:14:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:14:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:14:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:14:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:14:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:14:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:14:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:14:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:14:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:14:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:14:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:14:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:14:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:14:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:14:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:14:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:14:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:14:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:14:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:14:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:14:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:14:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:14:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:14:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:14:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:14:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:14:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:14:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:14:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:14:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:14:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:14:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:14:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:15:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:15:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:15:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:15:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:15:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:15:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:15:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:15:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:15:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:15:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:15:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:15:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:15:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:15:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:15:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:15:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:15:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:15:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:15:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:15:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:15:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:15:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:15:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:15:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:15:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:15:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:15:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:16:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:16:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:16:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:16:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:16:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:16:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:16:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:16:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:16:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:16:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:16:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:16:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:16:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:16:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:16:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:16:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:16:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:16:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:16:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:16:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:16:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:16:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:16:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:16:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:16:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:16:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:16:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:16:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:16:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:16:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:16:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:16:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:16:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:16:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:16:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:16:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:16:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:16:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:16:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:16:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:16:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:16:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:16:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:16:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:16:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:17:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:17:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:17:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:17:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:17:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:17:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:17:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:17:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:17:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:17:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:17:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:17:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:17:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:17:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:17:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:44 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:44 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:17:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:17:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:17:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:17:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:17:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:17:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:17:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2013 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:17:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:17:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:17:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:17:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:17:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:17:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:17:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:17:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:17:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:18:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:18:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:18:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:18:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:18:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:18:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:18:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:18:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:18:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:18:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:18:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:18:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:18:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:18:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:18:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:18:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:18:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=769 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:18:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:18:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:18:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:18:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:18:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:18:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:18:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:18:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:18:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:08 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:19:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:19:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=720 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:19:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:19:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:19:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:19:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:19:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:19:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:19:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:19:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:19:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:19:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:19:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:19:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:19:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:19:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:19:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:19:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:20:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:20:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:20:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:20:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=782 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=782 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:20:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:20:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:20:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:20:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:20:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:20:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:20:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:20:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:20:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:20:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:20:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:20:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:20:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:20:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:20:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:20:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:21:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:21:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:21:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:21:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:21:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:08 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:13 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:13 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:18 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:30 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 07:21:30 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 200
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 07:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:32 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 07:21:32 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 0
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=471 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:37 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 07:21:37 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 200
2024-11-28 07:21:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:21:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 07:21:39 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 0
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:39 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:39 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:44 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:45 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:45 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:21:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:21:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:21:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:21:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:21:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:21:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:21:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:21:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:21:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:21:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:21:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:21:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:21:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:22:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:22:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:22:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:05 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:22:10 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:22:11 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:22:12 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:22:13 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:22:20 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:21 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:22:22 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:22:23 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:22:33 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:34 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:22:35 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:22:36 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:22:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:22:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:22:44 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:22:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:22:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:22:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:22:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:22:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:22:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:22:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:22:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:22:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:22:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:22:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:22:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:22:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:22:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:22:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:22:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:23:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:23:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:23:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:23:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:05 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:23:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:23:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:23:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:23:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:23:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:23:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:23:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:23:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:23:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:23:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:23:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:23:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:31 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:23:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:23:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:23:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:23:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:23:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:23:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:23:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:23:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:23:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:23:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:23:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:23:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:23:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:23:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:23:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:23:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:08 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1736 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:44 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:44 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:24:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:24:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:24:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:24:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:24:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:24:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:24:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:24:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:24:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:25:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:25:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:25:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:25:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:25:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:25:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:25:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:26:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:26:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:26:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:26:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:26:13 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:26:14 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:26:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:26:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:26:22 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:26:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:26:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:26:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:26:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:26:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:26:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:26:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:26:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:26:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:26:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:26:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:26:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:26:39 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:26:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:26:42 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:26:43 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:26:44 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:26:45 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:26:51 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:26:52 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:52 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5212 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:26:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:26:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:26:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:26:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:26:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:27:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:27:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:27:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:27:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:27:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:27:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:27:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:27:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:27:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:27:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:27:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:27:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:27:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:27:19 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:27:20 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:27:21 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:27:22 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:27:30 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:27:31 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:27:32 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:27:33 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:27:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:27:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:27:35 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:27:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:36 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:27:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:37 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:27:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:38 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:27:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:27:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:27:39 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:27:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:27:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:27:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:27:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:27:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:27:44 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:27:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:27:45 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:27:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:27:45 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:27:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:27:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:27:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:27:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:27:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:27:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:27:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:27:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:27:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:48 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:27:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:27:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:27:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:27:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:27:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:27:50 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:27:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:27:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:27:53 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:27:54 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:27:55 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:27:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:27:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:27:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:27:59 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:28:00 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:28:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:28:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:28:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:28:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:28:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:28:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:28:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:28:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:28:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:28:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:28:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:28:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:28:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:28:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:28:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:28:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:28:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:28:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:28:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:28:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:28:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:28:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:28:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:28:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:28:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:28:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:28:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:28:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:28:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:28:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:28:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:28:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:28:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:28:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:28:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:28:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:28:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:28:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:28:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:28:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:28:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:28:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:28:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:28:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:28:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:28:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:28:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:28:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:28:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:28:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:28:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:28:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:28:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:28:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:28:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:28:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:28:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:28:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:28:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:28:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:28:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:28:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:28:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:28:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:28:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:28:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:28:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6719 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:28:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:28:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:28:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:28:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:28:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:48 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:28:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:28:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:28:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:28:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:28:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:28:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:28:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:28:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:28:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1048 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:28:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:29:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:29:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:29:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1505 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:29:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:29:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:29:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:29:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:29:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:29:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:54 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:29:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:29:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:29:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:29:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:29:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:30:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:30:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:30:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:39 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:44 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:44 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:44 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:44 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:44 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:44 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:45 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:45 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:30:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:30:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:30:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:30:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:30:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:30:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:30:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:30:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:30:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:30:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:30:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:31:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:31:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:31:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:31:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:31:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:31:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:31:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:31:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:31:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:31:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:31:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:31:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:31:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:31:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:31:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:31:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:31:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:31:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:31:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:31:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:31:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:31:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:31:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:31:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:31:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:31:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:31:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:31:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:31:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:31:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:31:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:31:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:31:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:31:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:31:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:31:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2901 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:31:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:31:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:31:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:31:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:31:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:31:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:31:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:31:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:32:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:32:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:32:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:32:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:32:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:32:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:32:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:32:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:32:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:32:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:32:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:32:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:32:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:32:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:32:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:32:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:32:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:32:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:32:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:32:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:32:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:32:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:32:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:32:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:32:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:32:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:32:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:32:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:32:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:32:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:32:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:32:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:32:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:32:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:32:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:32:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:32:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:32:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:32:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:32:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:32:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:32:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:32:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:32:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:32:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:32:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:32:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:32:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:32:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:32:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:32:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:32:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:32:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:32:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:32:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:32:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:32:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:32:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:32:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:33:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:33:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:33:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:33:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:33:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:33:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:33:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:33:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1865 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:33:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:33:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:33:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:33:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:33:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:33:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:33:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:33:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:33:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:33:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:33:44 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:33:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:33:44 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:33:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:33:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:33:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:33:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:33:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:33:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:33:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:33:52 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:33:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:33:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:33:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:33:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:33:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:34:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:34:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:34:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:34:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:34:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:34:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:34:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:34:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:34:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:34:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:34:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:34:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:34:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:34:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:34:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:34:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:34:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:34:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:34:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:34:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:34:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:34:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:34:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:34:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:34:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:34:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:34:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:34:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:34:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:34:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:34:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:34:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:35:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:35:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:35:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:35:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:35:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:35:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:35:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:35:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:35:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:35:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:35:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:35:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:35:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:35:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:35:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:35:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:35:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:35:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:35:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:35:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:35:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:35:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:35:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:35:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:35:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:35:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:35:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:35:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:35:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:35:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:35:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:35:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:35:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:35:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:35:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:35:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:35:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:35:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:35:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:35:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:35:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:35:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:35:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:35:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:35:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:36:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:36:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:36:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:36:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:36:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:36:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:36:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:36:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:36:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:36:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:36:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:36:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:36:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:36:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:36:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:36:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:36:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:36:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:36:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:36:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:36:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:36:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:36:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:36:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:36:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:36:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:36:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:36:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:36:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2730 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2730 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:36:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2730 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:36:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:36:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:36:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:36:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:36:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:37:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:37:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:37:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:37:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:37:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:37:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:37:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:37:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:37:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:37:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:37:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:37:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:37:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:37:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:37:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:37:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:37:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:37:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:37:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:37:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:37:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:37:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:37:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:37:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:37:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:37:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:37:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:37:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:37:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:37:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:37:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:37:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:37:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:37:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:37:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:37:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:37:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:37:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:37:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:37:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:37:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:37:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:37:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:38:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:38:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:38:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:05 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:38:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:38:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:38:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:38:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:38:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:38:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:38:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:38:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:38:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:38:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:38:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:38:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:38:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:38:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:38:26 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:38:27 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:38:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:38:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:38:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:38:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:38:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:38:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:38:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:38:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:38:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:38:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:38:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:38:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:38:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:38:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:38:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:39:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:39:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:39:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:39:08 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:39:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:39:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2304 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:39:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:39:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:39:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:39:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:39:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:39:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:39:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:39:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:39:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:39:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:39:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:39:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:39:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:39:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:39:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:39:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2517 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:39:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:39:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:39:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:39:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:39:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:39:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:39:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:39:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:39:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:39:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:39:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:39:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:39:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:39:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:39:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:39:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:40:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:40:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:40:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:40:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:40:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:40:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:40:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:40:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:40:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:40:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:40:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:40:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:40:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:40:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:40:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:40:12 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:40:13 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:40:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:40:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:40:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:40:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:40:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:40:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:40:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:40:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:40:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:40:26 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:40:27 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:40:28 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:40:29 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:40:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2509 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2510 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:40:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:40:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:40:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:40:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:40:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:40:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:40:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:40:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:40:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:40:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:40:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:40:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:40:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:40:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:40:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:40:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:40:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:40:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:40:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:40:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:41:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:41:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:41:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:41:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:03 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:41:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:41:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:41:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:41:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:41:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:41:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:41:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:41:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:41:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:41:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:41:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:41:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:41:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:41:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:41:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:41:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:41:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:41:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:41:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:41:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:41:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:41:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:41:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:41:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:41:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:41:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:41:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:41:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:41:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:41:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:41:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:41:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:41:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:42:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:42:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:42:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:42:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:42:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:42:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:42:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:42:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:42:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:42:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4529 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:42:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:42:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:42:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:42:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:42:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:42:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:42:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:42:47 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:42:48 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:42:49 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:42:50 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:42:51 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:42:52 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:42:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:42:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:42:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:42:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:42:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:43:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:43:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:43:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:43:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:43:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:43:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:43:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:43:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:43:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:43:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:43:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:43:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:43:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:43:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:43:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:43:18 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:43:19 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:43:20 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:43:21 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:43:22 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:43:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:43:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:43:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:43:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:43:26 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:43:39 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:43:40 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:43:41 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:43:42 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:43:43 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:43:44 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:43:45 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:43:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:43:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:43:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:43:46 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:43:47 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:44:01 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:44:02 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:44:03 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:44:04 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 07:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 07:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 07:44:05 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 07:44:06 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 07:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 07:44:07 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 07:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 07:44:08 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 07:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 07:44:09 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 07:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 07:44:10 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 07:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 07:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 07:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 07:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 07:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 07:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 07:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 07:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 07:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 07:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 07:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 07:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 07:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 07:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 07:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 07:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 07:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 07:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 07:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 07:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 07:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 07:44:20 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 07:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 07:44:21 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 07:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 07:44:22 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 07:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 07:44:23 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 07:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 07:44:24 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 07:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 07:44:25 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:26 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17542 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:44:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:44:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:44:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:44:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:44:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:44:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:44:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:44:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:44:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:44:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:44:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:44:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:44:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:44:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:44:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:44:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:44:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:44:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:44:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:44:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:44:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:44:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:45:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:45:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:45:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:45:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:02 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:45:03 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:45:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:45:04 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:45:05 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:45:06 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:12 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2932 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:45:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:45:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:45:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:45:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:45:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:45:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:45:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:45:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:45:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:45:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:45:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:45:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:45:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:45:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:45:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:45:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:45:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:45:43 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:43 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2995 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:45:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:45:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:45:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:45:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:45:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:45:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:45:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:45:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:45:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:45:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:45:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:46:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:46:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:46:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:46:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:46:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:46:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:46:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:46:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:46:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:46:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:46:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:46:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:46:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:46:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:46:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:46:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:46:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:46:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:46:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:46:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:46:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:46:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:46:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:46:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:46:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:46:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:46:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:46:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:46:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:46:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:46:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:46:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:46:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:46:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:46:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:46:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:46:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:46:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:46:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:46:42 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:46:43 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:46:44 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:46:45 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:46:46 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:46:47 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:46:48 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:46:49 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:46:50 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:46:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:46:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:47:02 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:47:03 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:47:04 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:47:05 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:47:06 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:47:07 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:47:08 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:47:09 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:47:10 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:47:11 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 07:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 07:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 07:47:25 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 07:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 07:47:26 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 07:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 07:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 07:47:27 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 07:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 07:47:28 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 07:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 07:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 07:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 07:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 07:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 07:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:47:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:47:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:47:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 07:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 07:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 07:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 07:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 07:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 07:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 07:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 07:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 07:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 07:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 07:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 07:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 07:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 07:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 07:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 07:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 07:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 07:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 07:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 07:47:41 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 07:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 07:47:42 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 07:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 07:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 07:47:43 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 07:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 07:47:44 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 07:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 07:47:45 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 07:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 07:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 07:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 07:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 07:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 07:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 07:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 07:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 07:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 07:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 07:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 07:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 07:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 07:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 07:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 07:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 07:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 07:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 07:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 07:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2024-11-28 07:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2024-11-28 07:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2024-11-28 07:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2024-11-28 07:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2024-11-28 07:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2024-11-28 07:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2024-11-28 07:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2024-11-28 07:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2024-11-28 07:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2024-11-28 07:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2024-11-28 07:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2024-11-28 07:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2024-11-28 07:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2024-11-28 07:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2024-11-28 07:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2024-11-28 07:48:02 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2024-11-28 07:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2024-11-28 07:48:03 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2024-11-28 07:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2024-11-28 07:48:04 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2024-11-28 07:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2024-11-28 07:48:05 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2024-11-28 07:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2024-11-28 07:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2024-11-28 07:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:48:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2024-11-28 07:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2024-11-28 07:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2024-11-28 07:48:08 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2024-11-28 07:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2024-11-28 07:48:09 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2024-11-28 07:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2024-11-28 07:48:10 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2024-11-28 07:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2024-11-28 07:48:11 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2024-11-28 07:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2024-11-28 07:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2024-11-28 07:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2024-11-28 07:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2024-11-28 07:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2024-11-28 07:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2024-11-28 07:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2024-11-28 07:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2024-11-28 07:48:15 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2024-11-28 07:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2024-11-28 07:48:16 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2024-11-28 07:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2024-11-28 07:48:17 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2024-11-28 07:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2024-11-28 07:48:18 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2024-11-28 07:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2024-11-28 07:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2024-11-28 07:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2024-11-28 07:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2024-11-28 07:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2024-11-28 07:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2024-11-28 07:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2024-11-28 07:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2024-11-28 07:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2024-11-28 07:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 25704
2024-11-28 07:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 25806
2024-11-28 07:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 25908
2024-11-28 07:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 26010
2024-11-28 07:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 26112
2024-11-28 07:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 26214
2024-11-28 07:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 26316
2024-11-28 07:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 26418
2024-11-28 07:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 26520
2024-11-28 07:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 26622
2024-11-28 07:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 26724
2024-11-28 07:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 26826
2024-11-28 07:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 26928
2024-11-28 07:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 27030
2024-11-28 07:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 27132
2024-11-28 07:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 27234
2024-11-28 07:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 27336
2024-11-28 07:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 27438
2024-11-28 07:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 27540
2024-11-28 07:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 27642
2024-11-28 07:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 27744
2024-11-28 07:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 27846
2024-11-28 07:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 27948
2024-11-28 07:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 28050
2024-11-28 07:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 28152
2024-11-28 07:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 28254
2024-11-28 07:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 28356
2024-11-28 07:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 28458
2024-11-28 07:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 28560
2024-11-28 07:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 28662
2024-11-28 07:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 28764
2024-11-28 07:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 28866
2024-11-28 07:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 28968
2024-11-28 07:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 29070
2024-11-28 07:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 29172
2024-11-28 07:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 29274
2024-11-28 07:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 29376
2024-11-28 07:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 29478
2024-11-28 07:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 29580
2024-11-28 07:48:41 [DEBUG] clck_gen.py:102 IND CLOCK 29682
2024-11-28 07:48:42 [DEBUG] clck_gen.py:102 IND CLOCK 29784
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:48:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:48:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:48:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:48:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:48:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:48:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:48:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:48:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:48:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:48:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:48:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:48:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:48:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:48:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:48:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:48:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:48:52 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:48:52 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:48:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:48:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:48:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:48:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:48:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:48:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:49:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:49:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:49:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:49:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:49:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:49:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:49:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:49:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:49:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:49:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:49:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:49:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:49:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:49:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:49:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:49:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:49:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:49:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:49:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:49:33 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:49:34 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:49:35 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:49:36 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:49:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:49:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:49:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:49:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:49:58 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:49:59 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:50:00 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:50:01 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:50:02 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:50:06 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:50:07 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:50:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:50:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:50:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:50:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:50:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:50:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:50:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:50:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:50:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:50:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:50:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:50:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:50:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:50:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:50:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:50:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:50:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:51:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:51:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:51:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:51:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:51:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:51:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:51:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:51:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3183 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3184 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:51:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:51:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:51:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:51:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:51:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:51:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:51:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:51:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:51:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:51:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:51:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:51:39 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:51:40 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:51:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:51:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:51:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:51:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:51:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:52:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:52:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:52:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:52:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:52:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:52:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:52:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=414 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=414 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=414 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=414 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=414 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=415 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:52:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:52:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:52:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:52:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:52:54 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:52:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:52:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:52:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:02 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=413 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:08 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=143 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=152 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=153 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=140 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=159 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=160 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:53:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:53:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:53:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:53:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:53:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:53:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:53:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:53:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:53:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:53:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:53:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:54:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:54:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:54:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:54:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:54:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:54:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:54:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:54:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:54:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:54:18 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:54:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:54:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:54:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:54:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:54:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:54:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:54:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:54:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:37 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:54:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:54:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:54:54 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.74.20:5700'
2024-11-28 07:54:54 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.74.20:5802)
2024-11-28 07:54:54 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.74.20:5801)
2024-11-28 07:54:54 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.74.22:6700'
2024-11-28 07:54:54 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.74.22:6802)
2024-11-28 07:54:54 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.74.22:6801)
2024-11-28 07:54:54 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.74.20:5700/1'
2024-11-28 07:54:54 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.74.20:5804)
2024-11-28 07:54:54 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.74.20:5803)
2024-11-28 07:54:54 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.74.20:5700/2'
2024-11-28 07:54:54 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.74.20:5806)
2024-11-28 07:54:54 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.74.20:5805)
2024-11-28 07:54:54 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.74.20:5700/3'
2024-11-28 07:54:54 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.74.20:5808)
2024-11-28 07:54:54 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.74.20:5807)
2024-11-28 07:54:54 [INFO] fake_trx.py:423 Init complete
2024-11-28 07:54:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:54:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:54:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:54:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:55:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:55:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:55:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:55:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:55:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:55:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 0 -> 1
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:55:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 0 -> 1
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:55:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 0 -> 1
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:55:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 0 -> 1
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:55:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:34 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.74.20:5700'
2024-11-28 07:56:34 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.74.20:5802)
2024-11-28 07:56:34 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.74.20:5801)
2024-11-28 07:56:34 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.74.22:6700'
2024-11-28 07:56:34 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.74.22:6802)
2024-11-28 07:56:34 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.74.22:6801)
2024-11-28 07:56:34 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.74.20:5700/1'
2024-11-28 07:56:34 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.74.20:5804)
2024-11-28 07:56:34 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.74.20:5803)
2024-11-28 07:56:34 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.74.20:5700/2'
2024-11-28 07:56:34 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.74.20:5806)
2024-11-28 07:56:34 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.74.20:5805)
2024-11-28 07:56:34 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.74.20:5700/3'
2024-11-28 07:56:34 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.74.20:5808)
2024-11-28 07:56:34 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.74.20:5807)
2024-11-28 07:56:34 [INFO] fake_trx.py:423 Init complete
2024-11-28 07:56:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 0 -> 1
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:56:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 0 -> 1
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:56:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 0 -> 1
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:56:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 0 -> 1
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:56:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:56:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:56:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:56:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:44 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:49 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:49 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:50 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:50 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:50 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:50 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:56:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:56:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:52 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:56:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:56:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:56:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:56:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:56:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:56:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:56:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 07:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
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2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 07:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
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2024-11-28 07:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
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2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
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2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:56:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:56:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:56:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:56:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=524 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:57:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:57:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:57:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:57:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:05 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:57:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:57:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:57:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:57:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:57:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:57:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:57:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:57:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:57:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:57:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:57:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:57:22 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:57:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:22 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:57:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:57:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:57:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:57:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:57:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:57:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:57:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:57:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:57:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:57:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:57:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:57:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:57:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:57:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:57:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:57:41 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:57:41 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:57:42 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:57:42 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:57:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:57:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:57:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:57:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 07:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 07:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 07:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 07:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 07:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:53 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 07:57:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 07:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 07:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 07:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 07:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 07:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 07:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 07:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 07:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:57:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:57:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 07:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 07:57:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 07:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 07:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 07:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 07:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 07:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 07:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 07:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:03 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=9034 tn=6 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 07:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 07:58:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 07:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 07:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 07:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 07:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 07:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 07:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 07:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 07:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 07:58:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 07:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 07:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 07:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 07:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 07:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 07:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 07:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:12 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:12 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 07:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 07:58:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 07:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 07:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 07:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 07:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 07:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 07:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 07:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 07:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:17 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 07:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 07:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 07:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 07:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 07:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 07:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 07:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:21 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:21 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:21 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 07:58:22 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 07:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 07:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 07:58:23 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 07:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 07:58:24 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 07:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 07:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 07:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 07:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 07:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 07:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 07:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 07:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:30 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 07:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 07:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 07:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 07:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 07:58:32 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 07:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 07:58:33 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:34 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 07:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 07:58:35 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 07:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 07:58:36 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 07:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 07:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 07:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 07:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:38 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:38 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 07:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 07:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 07:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 07:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 07:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 07:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 07:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 07:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 07:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 07:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 07:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 07:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 07:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 07:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 07:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 07:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:58:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:58:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 07:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 07:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 07:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 07:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 07:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 07:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 07:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 07:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:58:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:58:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:58:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:58:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:58:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:58:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:58:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:58:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:58:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:58:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:58:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:58:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:58:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:59:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:59:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:59:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:59:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:59:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:04 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:08 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:08 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:08 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:08 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:09 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:09 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:09 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:10 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:10 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:10 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:10 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:11 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:59:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:59:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:59:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:59:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:59:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:59:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:59:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:23 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:59:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:59:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:24 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:26 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 07:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 07:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 07:59:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 07:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 07:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 07:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 07:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 07:59:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:31 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 07:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:32 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:32 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 07:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 07:59:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 07:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:35 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:35 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 07:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 07:59:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:37 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:37 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 07:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:38 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:38 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 07:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 07:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 07:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:39 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:40 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 07:59:41 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:42 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:43 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 07:59:44 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:44 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:45 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:59:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:59:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 07:59:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 07:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 07:59:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 07:59:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 07:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 07:59:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 07:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 07:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 07:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 07:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 07:59:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 07:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 07:59:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 07:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 07:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 07:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 07:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 07:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 07:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 07:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 07:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 07:59:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 07:59:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 07:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 07:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:00:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:12 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:00:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:00:15 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:00:15 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:16 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:16 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:16 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:00:17 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:00:18 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:00:19 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:00:22 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:00:23 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:00:24 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:00:25 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:29 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:00:30 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:00:31 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:00:32 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:00:36 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:00:37 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:37 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:38 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:00:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 08:00:38 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 08:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 08:00:39 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 08:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 08:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 08:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 08:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 08:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 08:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 08:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 08:00:43 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 08:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 08:00:44 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 08:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 08:00:45 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 08:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:46 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:46 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:46 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 08:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 08:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 08:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 08:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 08:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 08:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 08:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 08:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:50 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:50 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:50 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 08:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 08:00:51 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 08:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 08:00:52 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 08:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 08:00:53 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 08:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 08:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:54 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:54 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 08:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 08:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 08:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 08:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 08:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 08:00:57 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 08:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 08:00:58 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:59 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:00:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:00:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:00:59 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 08:00:59 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 08:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 08:01:00 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 08:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 08:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 08:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 08:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:03 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:01:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 08:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 08:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 08:01:04 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 08:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 08:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 08:01:05 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 08:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 08:01:06 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:01:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:07 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 08:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 08:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 08:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 08:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 08:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 08:01:10 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 08:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:11 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:11 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:01:11 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 08:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 08:01:12 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 08:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 08:01:13 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 08:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 08:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 08:01:15 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:15 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:01:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:01:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=18563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:01:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:01:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:01:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:01:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:01:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:01:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:01:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:01:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:01:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:01:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:01:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:01:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:01:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:01:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:01:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:01:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:01:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:01:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:01:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:01:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:01:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:01:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:01:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:01:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:01:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:01:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:01:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:01:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:01:41 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:01:42 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:01:44 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:01:45 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:01:46 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:01:47 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:01:47 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:01:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:01:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:52 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:01:52 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:01:53 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:01:54 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:01:55 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:01:56 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:01:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:01:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:01:59 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:02:00 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:02:01 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:02 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:02:03 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:12 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 08:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 08:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 08:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 08:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 08:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 08:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:16 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:16 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 08:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 08:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 08:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 08:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 08:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 08:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 08:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 08:02:20 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 08:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 08:02:21 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:21 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:21 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 08:02:22 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 08:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 08:02:23 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 08:02:24 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 08:02:24 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 08:02:24 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 08:02:25 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:25 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 08:02:26 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 08:02:26 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 08:02:27 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 08:02:27 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 08:02:28 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 08:02:28 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 08:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 08:02:29 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 08:02:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:29 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:30 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 08:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 08:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 08:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 08:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 08:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 08:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 08:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 08:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 08:02:34 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 08:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 08:02:35 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 08:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 08:02:36 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 08:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 08:02:37 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 08:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:38 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:38 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:38 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 08:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 08:02:39 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 08:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 08:02:40 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 08:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 08:02:41 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 08:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 08:02:42 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 08:02:43 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 08:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 08:02:44 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 08:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 08:02:45 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 08:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 08:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 08:02:46 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 08:02:47 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 08:02:48 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 08:02:48 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 08:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 08:02:49 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 08:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 08:02:50 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 08:02:51 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:02:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:02:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:51 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 08:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 08:02:52 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 08:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 08:02:53 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 08:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 08:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 08:02:54 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 08:02:55 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:02:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:02:55 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:02:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:02:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:02:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:02:55 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:02:55 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=19521 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:03:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:03:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:03:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:03:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:03:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:03:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:03:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:03:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:07 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:12 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:13 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:13 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:14 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:03:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:03:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:18 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:18 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:03:19 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:19 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:03:20 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:20 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:03:21 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:22 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:22 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:22 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:23 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:23 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:23 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:03:24 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:03:25 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:26 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:26 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:03:26 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:27 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:27 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:03:28 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:29 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:29 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:29 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:03:30 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:03:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:03:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5405 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:03:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:03:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:03:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:03:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:03:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:03:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:03:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:03:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:03:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:03:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:03:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:03:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:03:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:03:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:03:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:03:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:03:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:03:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:03:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:03:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:03:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:03:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:03:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:03:51 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:03:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:03:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:03:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:03:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:03:57 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:03:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:03:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:03:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:03:58 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:03:58 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:03:59 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:04:00 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:01 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:01 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:01 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:04:02 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:04:03 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:04:04 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:04:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:05 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:04:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:04:05 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:04:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6417 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:04:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:04:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6417 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6417 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:05 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6417 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:04:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:04:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:04:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:04:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:04:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:04:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:04:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:04:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:04:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:04:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:04:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:04:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:04:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:04:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:04:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:04:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:04:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:04:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:04:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:04:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:04:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:04:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:04:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:04:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:23 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:04:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:04:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:04:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:26 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:26 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:04:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:04:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:04:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:30 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:04:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:04:32 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:04:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:33 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:04:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:34 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:35 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:04:35 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:04:36 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:04:37 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:38 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:04:39 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:04:40 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:04:41 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:04:42 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:04:43 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:04:44 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:04:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:45 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:46 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:46 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:04:47 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:04:48 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:49 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:49 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:04:50 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:04:51 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:04:52 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:04:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:53 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:53 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:04:53 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:04:54 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:04:55 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:56 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:04:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:04:56 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:56 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:04:57 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:04:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:04:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:04:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:04:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:04:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=10289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:05:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:05:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:05:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:05:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:05:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:05:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:05:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:05:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:05:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:05:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:05:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:05:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:05:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:05:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:05:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:05:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:05:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:05:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:05:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:05:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:05:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:05:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:05:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:05:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:05:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:05:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:05:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:05:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:05:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:05:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:05:25 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:05:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:05:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:05:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:05:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:05:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:05:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:05:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:05:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:05:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:05:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:05:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:05:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:05:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:05:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:05:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:05:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:05:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:05:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:05:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:05:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:05:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:05:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:05:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:05:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2900 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:05:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:05:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:05:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:05:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:05:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:05:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:05:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:05:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:05:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:05:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:05:52 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:05:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:05:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:53 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:05:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:05:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:54 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:05:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:55 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:05:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:05:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:05:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:05:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:05:58 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:05:59 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:05:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:05:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:05:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:05:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:05:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2218 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:06:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:06:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:06:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:05 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:06 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:06:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=711 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:06:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:06:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:06:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:06:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:06:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:06:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:06:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:06:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:06:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:06:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:06:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:06:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:06:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:06:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:06:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1304 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:06:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:06:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:06:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:06:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:06:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:06:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:06:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:06:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:06:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:06:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:06:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:06:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1202 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1202 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1202 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:42 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1202 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:06:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:06:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:06:52 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:06:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:06:52 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:06:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:06:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:06:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:06:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:06:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:06:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:06:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:06:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:06:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:06:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:06:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:06:59 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:07:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:07:01 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:07:02 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:07:03 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:07:04 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:07:05 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:07:05 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:07:06 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:07:07 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:07:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:07:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:07:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:07:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:07:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:07:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:07:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:07:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:07:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:07:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:07:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:07:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:07:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:07:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:07:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:07:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:07:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:07:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:07:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:07:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:07:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:07:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:07:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:07:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:07:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:07:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:07:40 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:07:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:07:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:07:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:07:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:07:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:07:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:07:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:07:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:07:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:07:53 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:07:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:07:54 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=352 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:07:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:07:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:07:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:08:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:08:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:08:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:08:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:08:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:08:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:08:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:08:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:08:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:08:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:08:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:08:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:08 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:08 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:08:08 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:08:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:09 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:08:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:08:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:08:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:08:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:08:15 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:16 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:08:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:08:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:08:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:08:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:08:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:08:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:08:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:08:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:08:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:08:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:08:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:08:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:08:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:08:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:08:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:08:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:08:33 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:08:34 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:08:35 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:08:36 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:08:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:08:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:08:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:08:40 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:08:41 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:08:42 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:08:43 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:08:44 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:08:45 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:08:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:08:46 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:08:47 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:08:48 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:08:49 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:08:50 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:08:51 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:08:52 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:08:53 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:08:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:08:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:08:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:08:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:08:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:08:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:08:59 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:08:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:09:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:09:01 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:02 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:09:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:09:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:09:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:09:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:09:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:09:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:08 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:09:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:09:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:09:14 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:14 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:09:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:09:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:09:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:09:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:09:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:09:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:09:18 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:09:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:09:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:09:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:09:21 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:09:22 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=1865 tn=4 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:22 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:22 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:09:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:09:27 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:09:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:09:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:28 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:09:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:09:28 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:09:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:09:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:09:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:09:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:09:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:09:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:09:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:36 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:09:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:09:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:09:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:09:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:09:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:09:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:09:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:09:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:09:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:09:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:09:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:09:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:09:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:09:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:09:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:09:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:09:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:09:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:09:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:09:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:09:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:09:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:09:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:09:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:09:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:09:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:09:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:10:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:10:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:10:02 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:10:03 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:10:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:10:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:10:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:10:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:10:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:10:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:10:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:10:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:10:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:10:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:10:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:10:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:10:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:10:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:10:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:10:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:10:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:10:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:10:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:10:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:10:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:10:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:10:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:10:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:10:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:10:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:10:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:10:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:10:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:10:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:10:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:10:25 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:10:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:10:26 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:10:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:10:27 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:10:28 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:10:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:10:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:10:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:10:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:10:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:10:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:10:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=126 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:34 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:10:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:10:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:10:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:10:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:10:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:10:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:10:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=132 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=135 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=138 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=141 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=144 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=147 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=150 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=153 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=156 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=159 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=162 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=165 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=171 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=174 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:41 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=177 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=180 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=183 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=186 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=189 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=192 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=195 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=198 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=201 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=204 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=210 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=213 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [ERROR] data_if.py:108 Failed to encode a TRXD message ('fn=216 tn=0 bl=148 rssi=-122 toa256=0') due to error: RSSI -122 is out of range
2024-11-28 08:10:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:10:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:10:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:10:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:10:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:10:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:10:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:10:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:10:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:10:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:10:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:10:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:10:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:10:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:10:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:10:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:10:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:10:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:10:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:10:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:10:57 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:10:58 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:10:59 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:11:00 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:11:01 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:11:02 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:11:03 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:11:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:11:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:11:04 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:11:05 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:11:06 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:11:07 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:11:08 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:11:09 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:11:10 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:11:11 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:11:12 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:11:13 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:11:14 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:11:15 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:11:16 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:11:17 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:11:18 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:11:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:11:19 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:11:19 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:11:20 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:11:21 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:11:22 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:11:23 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:11:24 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:11:25 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:11:26 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:11:27 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:11:28 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:11:29 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:11:30 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:11:31 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:11:32 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:11:33 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:11:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:34 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:11:35 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 08:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 08:11:36 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 08:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 08:11:37 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 08:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 08:11:38 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 08:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 08:11:39 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 08:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 08:11:40 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 08:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 08:11:41 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 08:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 08:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 08:11:42 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 08:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 08:11:43 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 08:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 08:11:44 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 08:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 08:11:45 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 08:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 08:11:46 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 08:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 08:11:47 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 08:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 08:11:48 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 08:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 08:11:49 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:11:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:11:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:11:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:11:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:11:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:11:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:11:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:11:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:11:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:11:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:11:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:11:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:11:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:11:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:11:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:11:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:11:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:11:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:11:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:12:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:12:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:12:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:12:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:12:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:12:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:12:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:12:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:12:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:12:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:12:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:12:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:12:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:12:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:12:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:12:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:12:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:12:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:12:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:12:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:12:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:12:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:12:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:12:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:12:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:12:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:12:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:12:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:12:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:12:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:12:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:12:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:12:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:12:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:12:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:12:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:12:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:12:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:12:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:12:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:12:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:12:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:12:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:12:33 [DEBUG] fake_trx.py:263 (MS@172.18.74.22:6700) Recv SETTA cmd
2024-11-28 08:12:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:12:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:12:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:12:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:12:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:12:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:12:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:12:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:12:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:12:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:12:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:12:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:12:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:12:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:12:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:12:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:12:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:12:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:12:47 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:12:48 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:12:49 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:12:50 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:12:51 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:12:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:12:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:12:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:12:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:12:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:12:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:12:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:12:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:12:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:12:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:13:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:13:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:13:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:13:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:13:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:13:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:13:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:13:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:13:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:13:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:13:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:08 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:13:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:13:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:13:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:13:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:13:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:13:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:13:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:13:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:13:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:13:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:13:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:13:20 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:13:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:13:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:13:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:13:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:13:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:13:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:13:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:13:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:13:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:13:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:13:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:13:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:13:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:13:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:13:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:13:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:13:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:13:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:13:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:13:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:13:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:13:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:13:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:13:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:13:54 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:13:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:13:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:13:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:13:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:13:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:13:58 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:13:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:13:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:13:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:14:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:01 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:14:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:14:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:14:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:14:03 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:14:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:14:04 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:04 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:14:05 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:14:06 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:14:07 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:14:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:14:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:14:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:14:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:14:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:14:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:14:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:14:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:14:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:14:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:14:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:14:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:14:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:14:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:14:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:14:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:14:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:14:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:14:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:14:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:14:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:14:22 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:14:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:14:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:14:25 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:14:26 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:14:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:14:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:14:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:14:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:14:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:14:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:14:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:14:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:14:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:14:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:14:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:14:32 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:14:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:14:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:14:34 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=560 tn=6 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:34 [WARNING] transceiver.py:250 (MS@172.18.74.22:6700) RX TRXD message (fn=560 tn=7 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:14:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:14:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:14:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:14:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:14:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:14:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:14:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:14:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:14:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:14:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:14:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:14:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:14:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:14:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:14:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:14:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:14:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:14:47 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:14:48 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:14:49 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:14:50 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:14:51 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:14:52 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:14:53 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:14:54 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:14:55 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:14:56 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:14:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:14:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:14:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:14:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:15:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:15:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:15:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:15:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:15:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:15:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:15:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:15:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:15:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:04 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:05 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:15:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:15:06 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:15:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:15:07 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:15:08 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:15:09 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:15:10 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:15:11 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:15:12 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:15:13 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:15:14 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:15:15 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:15:16 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:15:17 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:15:18 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:15:19 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:15:20 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:15:21 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:15:22 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:15:23 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:15:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:15:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:15:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:15:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:15:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:15:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:15:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:15:24 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4790 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:15:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:15:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:15:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:15:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:15:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:15:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:15:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:15:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:15:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:15:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:15:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:15:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:15:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:15:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:15:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:15:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:15:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:15:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:15:41 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:15:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:15:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:15:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:15:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:15:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:15:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:15:48 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:15:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:15:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:15:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:15:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:15:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:15:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:15:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:15:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:15:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:15:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:15:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:15:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:15:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:15:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:15:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:15:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:15:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:16:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:16:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:16:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:16:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:16:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:16:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:16:07 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:16:08 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:16:09 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:16:10 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:16:11 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:16:12 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:16:13 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:16:14 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:16:15 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:16:16 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:16:17 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:16:18 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:16:19 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:16:20 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:16:21 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:16:22 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:16:23 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:16:24 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:16:25 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:16:26 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:16:27 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:16:28 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:16:29 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:16:30 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:16:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:16:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:16:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:16:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7393 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:16:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:16:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7393 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:16:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7393 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:16:30 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7393 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:16:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:16:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:16:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:16:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:16:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:16:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:16:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:16:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:16:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:16:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:16:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:16:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:16:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:16:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:16:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:16:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:16:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:16:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:16:42 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:16:43 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:16:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:16:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:16:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:16:47 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:16:48 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:16:49 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:16:50 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:16:51 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:16:52 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:16:53 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:16:54 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:16:55 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:16:56 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:16:57 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:16:58 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:16:59 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:17:00 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:17:01 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:17:02 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:17:03 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:14 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:14 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:14 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:17:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:17:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:17:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:17:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:17:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:17:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:17:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:17:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:17:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:17:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:17:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:17:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:33 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:38 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:17:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:17:39 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:17:40 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:17:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:17:41 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:17:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:17:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:17:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:17:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:17:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:17:44 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:17:45 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:17:46 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:17:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:17:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:17:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:17:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:17:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:17:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:17:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:17:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:17:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:17:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:53 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:17:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:54 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:17:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:55 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:56 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:17:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:17:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:17:57 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:17:58 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:17:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:18:00 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:18:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:18:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:18:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:18:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:18:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:18:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:18:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:18:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:18:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:18:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:18:08 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:18:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:18:09 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:18:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:18:10 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:18:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:18:11 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:18:12 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:18:13 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:18:14 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:18:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:18:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:18:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:18:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:18:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:18:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:18:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:18:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:18:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:18:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:18:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:18:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:18:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:18:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:18:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:18:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:18:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:18:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:18:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:18:33 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:18:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:18:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:18:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:18:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:18:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:18:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:18:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:18:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:18:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:18:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:37 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:18:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:18:38 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:18:39 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:18:40 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:18:41 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:18:42 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:18:43 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:18:44 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:18:45 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:18:46 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:18:47 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:18:48 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:18:49 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:18:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3607 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:18:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3607 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:18:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3607 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:18:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3607 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:18:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:18:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:18:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:18:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:18:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:18:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:18:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:18:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:18:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:18:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:18:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:18:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:18:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:18:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:18:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:18:59 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:18:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:18:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:19:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:19:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:19:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:19:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:19:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:09 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:19:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:10 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:19:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:11 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:12 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:13 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:19:14 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:19:15 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:19:16 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:19:17 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:19:18 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:19:19 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:19:20 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:19:21 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:19:22 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:19:23 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:19:24 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:19:25 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:19:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:19:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:19:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:19:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:19:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:19:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:19:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:19:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:20:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:20:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:20:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:20:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:20:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:20:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:20:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:20:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:20:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:20:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:20:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:20:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:20:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:20:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:20:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:20:10 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:20:11 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:20:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:20:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:20:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:20:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:20:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:20:17 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:20:18 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:20:19 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:20:20 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:20:21 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:20:22 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:20:23 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:20:24 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:20:25 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:20:26 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:20:27 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:20:28 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:20:29 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:20:30 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:20:31 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:20:32 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:20:33 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:20:34 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:20:35 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:20:36 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:20:37 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:20:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:37 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:20:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:20:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:20:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:20:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:20:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:20:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:20:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:20:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:20:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:20:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:20:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:20:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:20:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:20:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:20:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:20:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:20:52 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:20:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:20:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:20:52 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:20:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:20:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:20:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:20:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:20:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:20:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:20:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:20:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:20:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1416 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:21:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:21:05 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:21:06 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:21:07 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:21:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:21:08 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:21:09 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:21:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:21:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:21:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:21:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:18 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:21:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:19 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:21:20 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:21:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:21:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:21:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:21:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:21:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:21:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:21:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:21:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:21:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:21:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:21:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:21:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:21:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:21:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:21:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:21:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:21:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:21:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:21:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:21:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:21:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:21:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:21:55 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:21:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:00 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:00 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:00 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:00 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:00 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:00 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:00 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:22:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:22:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:22:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:22:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:22:09 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:09 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:22:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:22:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:22:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:22:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:22:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:22:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:22:18 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:22:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:22:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:22:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:22:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:22:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:22:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:22:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:22:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:22:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:22:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:22:31 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:22:32 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:32 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:38 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:38 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:22:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:22:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:22:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:22:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:22:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:22:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:22:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:22:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:22:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:22:46 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:46 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:46 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1870 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:22:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:22:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:22:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:22:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:22:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:22:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:22:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:22:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:22:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:22:55 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:22:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:22:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:22:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:22:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:22:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:22:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:00 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:00 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1869 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:23:05 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:23:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:23:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:23:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:23:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:23:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:23:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:10 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1214 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:23:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:23:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:23:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:23:19 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:21 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1215 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:23:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=785 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:23:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:23:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:23:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:23:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:44 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:44 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:44 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:23:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:50 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:23:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:23:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:23:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:23:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:23:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:23:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:23:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:23:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:23:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:57 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:23:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:58 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:23:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:23:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:23:59 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:24:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:24:00 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:24:01 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:24:02 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:24:03 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:24:04 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:24:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:24:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:24:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:24:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:24:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:24:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:24:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:24:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:24:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:24:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:24:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:24:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:24:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:24:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:24:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:24:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:24:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:24:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:24:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:24:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:24:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:24:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:24:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:24:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:24:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:24:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:24:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:24:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:24:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:24:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:24:27 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:24:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:24:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:24:28 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:24:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1007 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:24:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:24:33 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:24:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:24:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:24:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:24:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:24:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:24:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:24:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:24:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:24:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:24:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:24:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:24:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:24:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:24:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:24:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:24:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:24:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:24:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:24:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:24:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:24:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:24:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:24:52 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:24:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:24:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:24:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:24:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:24:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:24:54 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:24:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:24:55 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:24:56 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:24:57 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:24:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:24:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:24:58 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:24:59 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:25:00 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:25:01 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:25:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:25:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:25:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:16 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:27 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:27 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:25:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:25:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=547 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:25:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:25:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:37 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:37 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:37 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:37 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:37 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:25:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:25:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:25:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:25:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:45 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:25:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:25:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:53 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:53 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:53 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:58 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:58 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:58 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:58 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:25:58 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:25:58 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:25:58 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:25:59 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:25:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:25:59 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:25:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:25:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:25:59 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:25:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:00 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:06 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:06 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:06 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:26:06 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:26:06 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:26:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:07 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:08 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:26:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:09 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:10 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=925 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:26:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:26:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:26:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:26:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:26:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:27 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:27 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=555 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:32 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:32 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:32 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:32 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:32 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:32 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:32 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:33 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:34 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:35 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:36 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=780 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:26:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:26:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:26:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:50 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:26:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:55 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:55 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:55 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:55 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:26:55 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:26:55 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:55 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:26:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:26:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:26:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:26:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:26:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:26:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:26:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:01 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:01 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:01 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:12 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:17 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:17 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:17 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:17 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:17 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:17 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:17 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:18 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:27:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:24 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:27:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:27:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:27:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:27:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:27:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:40 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:45 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:27:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:27:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:27:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:27:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:27:57 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 08:27:57 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 200
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:27:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:27:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:58 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 08:27:58 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 0
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:27:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:27:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:27:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:27:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=467 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:28:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:28:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:28:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:28:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:28:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:04 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 08:28:04 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 200
2024-11-28 08:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 08:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:28:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:28:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] fake_trx.py:376 (BTS@172.18.74.20:5700) Recv FAKE_TRXC_DELAY cmd
2024-11-28 08:28:06 [INFO] fake_trx.py:379 (BTS@172.18.74.20:5700) Artificial TRXC delay set to 0
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD FAKE_TRXC_DELAY
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=469 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=470 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:28:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:28:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:28:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:28:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:28:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:28:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:28:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:28:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:28:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:28:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:28:22 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:28:22 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:28:22 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:22 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:23 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:28:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:24 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:25 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:26 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:28:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:28:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:28:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:28:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:28:27 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:28:28 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:28:29 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:28:30 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:28:31 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:32 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:33 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:33 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:28:34 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:28:35 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:36 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:36 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:36 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:36 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:36 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:28:37 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:28:38 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:39 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:39 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:39 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:28:40 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:28:41 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:42 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:28:43 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:44 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:28:45 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:28:46 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:47 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:28:48 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:28:49 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:50 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:28:51 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:28:52 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:53 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:28:54 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:54 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:54 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:28:55 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:28:56 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:57 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:57 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:58 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:28:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:28:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:28:58 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:28:58 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:28:59 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:29:00 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:01 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:01 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:01 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:29:02 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:29:03 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:04 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:04 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:29:05 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:29:06 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:29:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:29:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:29:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:29:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:13 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:13 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:13 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:13 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:29:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:29:18 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:29:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:29:19 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:29:19 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:19 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:19 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:20 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:20 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:29:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:29:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:29:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:29:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:26 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:26 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:28 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:29:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:29:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:29:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:29:28 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:29:33 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:29:33 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:29:33 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:29:33 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:29:33 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:34 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:35 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:29:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:29:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:29:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:29:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:29:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:29:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:29:45 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:29:46 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:29:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:29:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:29:46 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:29:47 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:29:48 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:29:49 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:29:50 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:29:51 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:29:52 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:29:53 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:29:54 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:29:55 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:29:56 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:29:57 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:29:58 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:29:59 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:30:00 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:30:01 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:30:02 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:30:03 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:30:04 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:30:05 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:30:06 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:30:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:30:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:30:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:30:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:30:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:30:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:30:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:30:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:30:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:30:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:30:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:30:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:14 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:30:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:16 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:30:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:30:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:30:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:30:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:30:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:30:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:30:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:30:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:30:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:30:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:30:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:30:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:30:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:30:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:30:31 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:30:32 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:30:33 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:30:34 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:30:35 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:30:36 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:30:37 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:37 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:30:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:30:37 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:30:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:30:42 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:30:42 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:30:42 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:30:42 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:30:42 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:30:42 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:30:42 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:30:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:30:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:43 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:30:44 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:30:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:30:45 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:30:46 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:30:47 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:30:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:30:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:48 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:48 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:30:49 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:50 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:50 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:50 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:30:51 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:30:52 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:53 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:30:54 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:55 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:30:56 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:57 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:57 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:30:58 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:59 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:30:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:30:59 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:30:59 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:30:59 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:31:00 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:31:01 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:31:02 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:31:03 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:31:04 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:31:05 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:31:06 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:31:07 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:31:08 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:31:09 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:31:10 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:31:11 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:31:12 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:31:13 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:31:14 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:31:15 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:31:16 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:31:17 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:31:18 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=7894 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:31:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:31:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:31:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:31:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:31:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:24 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=379 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:31:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:31:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:31:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:31:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:32 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:31:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:34 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:35 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:31:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=904 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:31:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:31:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:31:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:31:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:40 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:31:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:31:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:31:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:31:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:31:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:31:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:31:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:52 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:52 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:31:53 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:53 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:31:54 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:55 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:31:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:31:55 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:55 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:31:56 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:31:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:31:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:31:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:31:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:31:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:10 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:10 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:11 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:18 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:24 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:24 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=445 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:25 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=445 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:31 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:32 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:33 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:35 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:35 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:40 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:40 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:40 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:41 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:42 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:32:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:43 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:49 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:32:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:32:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:50 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:50 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:51 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:32:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:32:52 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:52 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:32:53 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:32:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:32:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:32:54 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:32:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:32:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:32:59 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:00 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:00 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:00 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:00 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:00 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:33:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:01 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:02 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:33:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:09 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:33:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:33:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:33 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:34 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:34 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:36 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:36 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:36 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:36 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:37 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:37 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:38 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:38 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:38 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:39 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:39 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:39 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:39 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:40 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:40 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:40 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:41 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:41 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:42 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:42 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:43 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:44 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:44 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:45 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:45 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:33:45 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:46 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:46 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:33:46 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:33:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:33:47 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:53 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:53 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:53 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:53 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:53 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:33:53 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:33:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:33:53 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:53 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:53 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:54 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:54 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:59 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:59 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:59 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:59 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:33:59 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:33:59 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:33:59 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:34:00 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:34:01 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:34:02 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:34:03 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:34:04 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:34:05 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:34:06 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:34:07 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:34:08 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:34:09 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:34:10 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:34:11 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:34:12 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:34:13 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:34:14 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:34:15 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:34:16 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:34:17 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:34:18 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:34:19 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:34:20 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:34:21 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:34:22 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:34:23 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:34:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:34:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:34:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:34:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:34:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:23 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5226 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:34:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:34:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:34:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:34:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:34:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:34:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:34:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:34:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:34:30 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:34:31 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:34:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:34:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:34:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:34:35 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:34:36 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:34:37 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:34:38 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:34:39 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:34:40 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:34:41 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:34:42 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:34:43 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:34:44 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:34:45 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:34:46 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:34:47 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:34:48 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:34:49 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:34:50 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:34:51 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:34:52 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:34:53 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:34:54 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:34:55 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:34:56 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:34:57 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:34:58 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:34:59 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:35:00 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:35:01 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:35:02 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:35:03 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:35:04 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:35:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:05 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:35:06 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:35:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:35:07 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:35:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:35:08 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:35:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:35:09 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:35:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:35:10 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:35:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:35:10 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:35:15 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:35:15 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:35:15 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:35:15 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:35:15 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:35:15 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:15 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:35:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:35:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:16 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:35:17 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:35:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:35:18 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:35:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:35:19 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:35:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:35:20 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:35:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:35:22 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:35:23 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:24 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:35:24 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:35:25 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:35:26 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:35:27 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:35:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:35:28 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:35:28 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:35:29 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:35:30 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:35:31 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:31 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:35:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:35:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3454 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:35:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:35:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:35:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:35:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:35:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:35:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:35:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:35:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:35:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:37 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:35:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:35:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:38 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:35:38 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:35:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:35:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:35:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:35:40 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:35:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:35:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:35:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:35:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:35:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:35:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:35:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:35:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:35:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:35:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:35:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:35:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:35:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:44 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:35:44 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:35:45 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:45 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:35:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:35:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:46 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:35:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:35:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:35:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:35:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:35:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:35:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:35:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:35:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:35:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:35:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:35:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:35:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:35:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:52 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:35:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:52 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:35:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:35:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:35:52 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:35:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:35:53 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:53 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:35:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:35:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:54 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:35:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:35:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:35:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:35:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:35:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:56 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:35:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:35:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:35:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:35:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:35:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:35:59 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:35:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:36:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:36:00 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:00 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:00 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:36:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:36:01 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:01 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:36:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:36:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:02 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:36:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:36:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:36:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:03 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:36:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:36:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:04 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:36:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:36:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:05 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:36:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:36:06 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:06 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:36:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:07 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:36:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:07 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:36:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:36:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:36:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:36:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:36:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:36:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:36:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:36:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:36:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1518 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:36:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:36:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:36:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:36:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:36:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:36:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:36:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:27 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:36:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:36:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:28 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:36:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:29 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:29 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1052 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1052 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1052 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1052 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:29 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1052 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:34 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:34 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:34 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:34 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:36:34 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:36:34 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:34 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:36:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:36:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:35 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:36 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:37 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:36:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:38 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:39 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:36:40 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:36:41 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:41 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1496 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:36:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:36:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:36:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:36:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:36:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:36:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:36:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:49 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:36:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:36:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:36:51 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:36:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:36:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:36:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:36:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:36:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:36:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:36:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:36:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:36:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:36:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:36:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:36:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:36:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=595 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:37:04 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:13 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:18 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:18 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:18 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:18 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:18 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:18 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:18 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:18 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:18 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:18 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:18 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:25 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:37:32 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:36 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:47 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:47 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:47 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:47 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:37:47 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:48 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:49 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:37:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:50 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1005 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:51 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1006 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:37:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:37:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:37:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:37:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:37:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:37:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:37:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:37:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:37:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:37:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:37:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:04 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=292 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:16 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:16 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:16 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:16 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:16 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:38:16 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:17 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=320 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=320 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=321 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:22 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:23 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:23 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:23 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:23 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:23 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:23 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:23 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:28 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:28 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:28 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:28 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:28 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:28 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:28 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:38:29 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:29 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:35 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:35 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:35 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:35 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:36 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:38:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=623 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:38:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:38:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:38:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:38:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:38:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:38:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:38:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:38:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:38:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:38:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:38:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:38:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:38:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:38:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:38:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:38:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:38:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:38:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:38:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:39:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:39:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:39:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:39:02 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:39:03 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:39:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:39:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:39:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:39:07 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:39:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:39:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:39:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:39:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:39:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:39:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:39:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:39:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:39:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:39:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:39:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:39:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:39:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:22 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:39:27 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:39:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:39:27 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:39:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:39:27 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:39:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:39:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:39:29 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:39:30 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:39:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:39:31 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:39:32 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:39:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:39:33 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:39:34 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:39:35 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:39:36 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:39:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2079 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:39:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2079 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:39:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2079 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:39:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2079 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:39:36 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2079 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:39:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:39:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:39:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:39:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:39:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:39:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:39:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:39:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:39:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:39:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:39:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:39:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:39:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD NOHANDOVER
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:39:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:39:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:39:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:39:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:39:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:39:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:39:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:39:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:39:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:39:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:39:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:39:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:39:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:39:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:39:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:39:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:40:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:40:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:40:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:40:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:40:05 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:40:06 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:06 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2289 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:11 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:16 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:16 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:16 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:16 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:16 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:16 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:16 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:40:17 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:40:17 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:40:17 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:40:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:40:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:40:17 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:40:18 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:40:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:40:19 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:40:20 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:40:21 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:40:22 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:40:23 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:40:24 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:40:25 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:40:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:40:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:40:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:40:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:40:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:40:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:40:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:40:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:40:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:40:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:40:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:40:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:40:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:40:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:40:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:40:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:44 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:44 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:44 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1864 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:49 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:49 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:49 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:49 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:49 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:40:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:40:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:40:54 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:40:54 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:40:54 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:40:54 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:40:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:40:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:55 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:40:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:56 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:57 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:40:58 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:40:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:40:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:40:59 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:41:00 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:41:01 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:41:02 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:41:13 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:41:13 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:41:13 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:41:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:41:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:41:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:41:15 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:41:16 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:41:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:41:17 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:41:18 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:41:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:41:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:41:21 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:41:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:41:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:41:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:41:32 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:41:32 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:41:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:34 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:35 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:41:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:36 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:41:37 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:41:38 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:41:39 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:41:40 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:41:41 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:41:42 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:41:43 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:41:44 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:41:45 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:41:46 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:51 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:56 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:56 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:56 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:56 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:41:56 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:41:56 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:41:56 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:41:56 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:41:56 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:41:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:41:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:41:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:57 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:58 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:41:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:41:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:41:59 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:42:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:42:00 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:42:01 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:42:02 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:42:03 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:42:04 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:42:15 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:42:15 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:42:15 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:42:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:42:15 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:42:16 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:42:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:42:17 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:42:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:42:18 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:42:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:42:19 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:42:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:42:20 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:42:21 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:42:22 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:42:23 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:42:24 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:42:25 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:35 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:35 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:35 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:35 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:35 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:35 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:35 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:42:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:42:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:42:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:42:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:42:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:36 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:37 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:42:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:38 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:39 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:40 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:42:41 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:42:42 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:42:43 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:42:44 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:42:45 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:42:46 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:47 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:52 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:52 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:52 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:52 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:52 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:42:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:42:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:42:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:42:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:42:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:42:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:42:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:42:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:42:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:42:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:42:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:42:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:43:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:43:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:43:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:43:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:43:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:43:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:43:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:43:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:43:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:43:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:43:08 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:43:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:43:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:43:11 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:43:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:43:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:43:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:43:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:43:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:43:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:43:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:17 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:17 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:17 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:17 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4477 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:22 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:22 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:22 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:22 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:43:22 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:22 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:22 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:22 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:27 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:27 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:27 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:27 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:43:27 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:43:27 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:27 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:43:28 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:43:28 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:43:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:43:28 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:43:28 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:43:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:43:29 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:43:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:43:30 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:43:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:43:31 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:43:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:43:32 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:43:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:43:33 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:43:34 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:43:35 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:43:36 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:43:37 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:43:38 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:43:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:43:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:43:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:43:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:43:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:43:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:43:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:43:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:43:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:43:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:43:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:43:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:43:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:43:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:43:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:43:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:43:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:43:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:43:57 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:43:58 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:43:59 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:44:00 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:01 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2724 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:44:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:44:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:44:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:44:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:44:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:44:11 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:44:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:44:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:44:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:44:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:44:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:44:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:44:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:44:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:44:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:44:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:44:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:44:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1866 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:44:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:44:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:44:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:44:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:44:30 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:44:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:44:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:44:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:44:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:44:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:44:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:44:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:44:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:38 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1860 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1860 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:44:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:44:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:44:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:44:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:44:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:44:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:44:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:44:49 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:44:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:50 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:44:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:51 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:44:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:52 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:44:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:53 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:44:54 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:44:55 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:44:56 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:44:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:44:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:44:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:44:57 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:44:57 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:02 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:02 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:02 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:02 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:02 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:02 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:02 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:02 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:07 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:07 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:07 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:07 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:07 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:45:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:45:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:45:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:45:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:45:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:45:07 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:45:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:08 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:45:09 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:45:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:45:10 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:45:11 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:45:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:45:12 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:45:13 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:45:14 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:45:15 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:15 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:45:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:45:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:45:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:45:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:45:26 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:45:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:45:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:45:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:45:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:45:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:45:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:45:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:45:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:45:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:45:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:45:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:45:35 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:45:36 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:45:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:45:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:45:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:45:40 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:40 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:45 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:50 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:50 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:50 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:50 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:45:50 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:45:50 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:45:50 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:45:50 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:45:50 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:45:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:45:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:45:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:51 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:45:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:52 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:45:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:53 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:45:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:54 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:45:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:55 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:45:56 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:45:57 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:45:58 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:45:59 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:45:59 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:45:59 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:45:59 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:45:59 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:45:59 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1867 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:09 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:46:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:46:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:46:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:46:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:46:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:46:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:46:10 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:46:11 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:46:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:46:12 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:46:13 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:46:14 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:46:15 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:46:16 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:46:17 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:46:18 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:46:19 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:46:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2296 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2296 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=2297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:46:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:46:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:46:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:46:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:46:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:46:30 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:46:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:46:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:46:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:46:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:46:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:46:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:46:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:46:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:46:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:46:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:46:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:46:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:46:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:46:41 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:46:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:46:41 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:46:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:46 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:51 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:51 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:51 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:51 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:46:51 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:46:51 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:46:51 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:46:51 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:46:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:46:51 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:46:51 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:46:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:52 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:46:53 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:53 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:53 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:46:54 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:54 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:54 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:46:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:55 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:46:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:46:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:46:56 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:46:57 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:46:58 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:46:59 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:47:00 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:47:01 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:47:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:47:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:47:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:47:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:47:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:47:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:47:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:47:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:47:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:47:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:47:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:47:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:47:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:47:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:47:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:47:17 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:17 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:47:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:47:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:47:19 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:47:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:47:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:47:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:47:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:47:24 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:47:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:47:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:47:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:47:30 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:47:30 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:47:30 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:47:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:47:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:47:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:47:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:47:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:47:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:47:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:47:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:47:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:47:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:47:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:47:39 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:47:40 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:47:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:41 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:47:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:46 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:46 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:46 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:46 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:47:46 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:47:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:47:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:47:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:47:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:47:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:47:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:47:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:47:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:47:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:47:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:47:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:47:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:47:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:47:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:47:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:47:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:47:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:47:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:47:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:47:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:48:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:48:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:01 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:48:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:06 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:06 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:06 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:06 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:48:06 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:48:06 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:06 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:48:07 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:48:07 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:48:07 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:07 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:07 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:07 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:07 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:07 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:07 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:12 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:12 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:12 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:12 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:48:12 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:48:12 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:48:12 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:48:12 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:48:12 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:48:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:12 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:48:13 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:48:13 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:13 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:48:14 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:14 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:14 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:19 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:19 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:19 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:19 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:48:19 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:48:19 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:19 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:48:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:48:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:20 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:20 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:48:21 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:48:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:48:22 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:48:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:48:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:23 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:48:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:24 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:48:25 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:25 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:48:26 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:48:27 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:48:28 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:48:29 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:30 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:48:30 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:48:31 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:48:32 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:48:33 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:48:34 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:35 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:35 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:48:35 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:35 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:35 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:48:36 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:48:37 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:48:38 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:48:39 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:48:40 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:40 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:48:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:48:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:48:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:48:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:48:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:48:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:46 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:47 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:48 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:48:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:48:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:48:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:48:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:48:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:48:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:48:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:48:54 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:48:55 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:56 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:48:56 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:48:56 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:56 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:48:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:48:57 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:48:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:48:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:49:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:01 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:01 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:49:01 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:01 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:49:01 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:49:02 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:49:03 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:49:04 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:49:05 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:49:06 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:06 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:06 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:49:06 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:49:06 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:49:06 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:49:11 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:49:11 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:49:11 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:49:11 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:49:11 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:49:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:49:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:49:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:49:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:49:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:49:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:49:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:16 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:17 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:17 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:49:17 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:17 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:49:17 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:49:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:49:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:49:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:49:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:22 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:22 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:22 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:22 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:49:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:49:23 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:49:24 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:49:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:49:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:49:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:49:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:49:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:49:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:49:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:49:31 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:49:32 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:32 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:49:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:49:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:49:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:49:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:49:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:49:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:49:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:49:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:49:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:49:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:49:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:49:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:49:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:49:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:49:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:49:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:49:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:49:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:49:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:47 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:47 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:47 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:47 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:49:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:49:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:49:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:49:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:49:52 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:49:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:49:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:49:53 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:49:53 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:53 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:49:53 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:49:54 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:49:55 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:49:56 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:49:57 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:49:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:49:58 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:49:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:49:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:49:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:50:03 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:50:03 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:50:03 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:50:03 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:50:03 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:50:03 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:50:03 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:50:03 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:03 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:50:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:50:04 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:50:05 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:05 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:05 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:50:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:50:05 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:50:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:50:10 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:50:10 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:50:10 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:50:10 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:50:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:50:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:50:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:50:11 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:50:11 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:50:11 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:11 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:50:12 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:50:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:50:13 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:50:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:50:14 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:50:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:50:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:50:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:50:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:50:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:50:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:50:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:50:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:50:18 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:50:19 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:50:20 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:50:21 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:50:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:50:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:50:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:50:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:50:26 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:50:27 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:50:28 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:50:29 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:50:30 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:50:31 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:50:31 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:50:32 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:50:33 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:50:34 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:50:35 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:50:36 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:50:37 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:50:38 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:50:39 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:50:40 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:50:41 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:50:42 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:50:43 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:50:44 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:50:45 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:50:46 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:50:47 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:50:48 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:50:49 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:50:50 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:51 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:50:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:50:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:50:51 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:50:52 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:50:53 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:50:54 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:50:55 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:50:56 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:50:57 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:50:58 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 08:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 08:50:59 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 08:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 08:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 08:51:00 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 08:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 08:51:01 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 08:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 08:51:02 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 08:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 08:51:03 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 08:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 08:51:04 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 08:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 08:51:05 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 08:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 08:51:06 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 08:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 08:51:07 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 08:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 08:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 08:51:08 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 08:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 08:51:09 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 08:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 08:51:10 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 08:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:11 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:11 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 08:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 08:51:12 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 08:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 08:51:13 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 08:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 08:51:14 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 08:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 08:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 08:51:15 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 08:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 08:51:16 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 08:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 08:51:17 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 08:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 08:51:18 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 08:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 08:51:19 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 08:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 08:51:20 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 08:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 08:51:21 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 08:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 08:51:22 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 08:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 08:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 08:51:23 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 08:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 08:51:24 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 08:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 08:51:25 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 08:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 08:51:26 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 08:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 08:51:27 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 08:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 08:51:28 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 08:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 08:51:29 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 08:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 08:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 08:51:30 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 08:51:31 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:31 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:51:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:51:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:51:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17577 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:51:31 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=17577 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:51:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:51:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:51:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:51:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:51:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:51:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:51:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:51:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:51:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:51:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:51:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:51:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:51:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:51:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:51:42 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:51:42 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:43 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:51:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:51:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:51:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:51:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:51:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:51:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:51:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:51 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:51 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:51 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:51 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:51:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:51:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:54 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:54 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:51:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:51:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:57 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:51:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:51:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:51:57 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:51:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:51:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:51:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:00 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:00 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:00 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:00 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:05 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:05 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:05 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:05 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:52:05 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:52:05 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:52:05 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:52:05 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:05 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:05 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:05 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:52:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:52:06 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:52:07 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:08 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:08 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:08 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:08 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:52:09 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:52:10 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:10 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:52:10 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:52:11 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:12 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:52:12 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:52:13 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:52:14 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:15 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:52:15 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:52:16 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:52:16 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:52:17 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:52:18 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:18 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:18 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:18 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:18 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:18 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:23 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:23 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:23 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:23 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:52:23 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:52:23 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:23 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:52:24 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:52:24 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:52:24 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:24 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:24 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:24 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:25 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:25 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:26 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:27 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:28 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:28 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:52:29 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:52:30 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:30 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:30 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:30 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:52:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:52:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:52:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:52:36 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:52:36 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:52:36 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:36 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:37 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:37 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:52:38 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:52:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:52:39 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:40 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:52:40 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:52:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:52:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:52:41 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:52:42 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:52:43 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:44 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:52:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:52:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:52:44 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:52:45 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:52:46 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:52:47 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:52:48 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:52:49 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:52:50 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:52:51 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:52:52 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:52:53 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:52:54 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:52:55 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:52:56 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:52:57 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:52:58 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:52:59 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:53:00 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:53:01 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:53:02 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:53:03 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:53:04 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:04 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:53:04 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:53:04 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:53:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:53:09 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:53:09 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:53:09 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:53:09 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:53:09 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:53:09 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:53:09 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:53:09 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:53:09 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:53:10 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:53:10 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:53:10 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:53:10 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:10 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:10 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:10 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:10 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:11 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:11 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:53:11 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:11 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:53:11 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:12 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:12 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:12 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:12 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:53:12 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:53:13 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:13 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:53:13 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:53:14 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:53:14 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:53:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:53:15 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:53:16 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:53:17 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:53:18 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:53:19 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:53:20 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:53:21 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:53:22 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:53:23 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:53:24 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:53:25 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:53:26 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:53:27 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:53:28 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:53:29 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:53:30 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:53:31 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:53:32 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:53:33 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:34 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:34 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:53:34 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:53:34 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:53:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:53:34 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:53:34 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=5261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:53:39 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:53:39 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:53:39 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:53:39 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:53:39 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:53:39 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:53:39 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:39 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:53:39 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:53:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:40 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:41 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:42 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:42 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:53:42 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:42 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:53:42 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:53:43 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:53:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:53:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:53:44 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:45 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:45 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:45 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:45 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:53:45 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:53:46 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:53:47 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:53:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:53:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:53:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:53:48 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:53:49 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:53:50 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:53:51 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:53:52 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:53:53 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:53:54 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:53:55 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:53:56 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:53:57 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:53:58 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:53:59 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:54:00 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:54:01 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:54:02 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:54:03 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:54:04 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:54:05 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:54:06 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:54:07 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:54:08 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:08 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:08 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:54:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:54:08 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:54:13 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:54:13 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:54:13 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:54:13 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:54:13 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:54:13 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:13 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:54:14 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:54:14 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:54:14 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:14 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:14 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:15 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:54:15 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:15 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:16 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:16 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:54:16 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:54:16 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:16 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:54:21 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:54:21 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:54:21 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:54:21 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:54:21 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:54:21 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:54:21 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:54:21 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:21 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:21 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:21 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:54:22 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:22 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:54:22 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:54:23 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:23 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:23 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:23 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:54:23 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:54:24 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:24 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:54:24 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:54:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:54:25 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:54:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:54:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:54:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:54:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:54:26 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:54:27 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:54:28 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:54:29 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:54:30 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:54:31 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:54:32 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:54:33 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:54:34 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:54:35 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:54:36 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:54:37 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:54:38 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:54:39 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:54:40 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:54:41 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:54:42 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:54:43 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:54:44 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:54:45 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:54:46 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:54:47 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:54:48 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:54:49 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:54:50 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:54:51 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:54:52 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:54:53 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:54:54 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:54:54 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:54:54 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:54 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:54:54 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:54:55 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:54:56 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:54:57 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:54:58 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:54:59 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:55:00 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:55:01 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:55:02 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:55:03 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:55:04 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:55:05 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:55:06 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:55:07 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:55:08 [DEBUG] clck_gen.py:102 IND CLOCK 10404
2024-11-28 08:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 10506
2024-11-28 08:55:09 [DEBUG] clck_gen.py:102 IND CLOCK 10608
2024-11-28 08:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 10710
2024-11-28 08:55:10 [DEBUG] clck_gen.py:102 IND CLOCK 10812
2024-11-28 08:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 10914
2024-11-28 08:55:11 [DEBUG] clck_gen.py:102 IND CLOCK 11016
2024-11-28 08:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 11118
2024-11-28 08:55:12 [DEBUG] clck_gen.py:102 IND CLOCK 11220
2024-11-28 08:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 11322
2024-11-28 08:55:13 [DEBUG] clck_gen.py:102 IND CLOCK 11424
2024-11-28 08:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 11526
2024-11-28 08:55:14 [DEBUG] clck_gen.py:102 IND CLOCK 11628
2024-11-28 08:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 11730
2024-11-28 08:55:15 [DEBUG] clck_gen.py:102 IND CLOCK 11832
2024-11-28 08:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 11934
2024-11-28 08:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 12036
2024-11-28 08:55:16 [DEBUG] clck_gen.py:102 IND CLOCK 12138
2024-11-28 08:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 12240
2024-11-28 08:55:17 [DEBUG] clck_gen.py:102 IND CLOCK 12342
2024-11-28 08:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 12444
2024-11-28 08:55:18 [DEBUG] clck_gen.py:102 IND CLOCK 12546
2024-11-28 08:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 12648
2024-11-28 08:55:19 [DEBUG] clck_gen.py:102 IND CLOCK 12750
2024-11-28 08:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 12852
2024-11-28 08:55:20 [DEBUG] clck_gen.py:102 IND CLOCK 12954
2024-11-28 08:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 13056
2024-11-28 08:55:21 [DEBUG] clck_gen.py:102 IND CLOCK 13158
2024-11-28 08:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 13260
2024-11-28 08:55:22 [DEBUG] clck_gen.py:102 IND CLOCK 13362
2024-11-28 08:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 13464
2024-11-28 08:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 13566
2024-11-28 08:55:23 [DEBUG] clck_gen.py:102 IND CLOCK 13668
2024-11-28 08:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 13770
2024-11-28 08:55:24 [DEBUG] clck_gen.py:102 IND CLOCK 13872
2024-11-28 08:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 13974
2024-11-28 08:55:25 [DEBUG] clck_gen.py:102 IND CLOCK 14076
2024-11-28 08:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 14178
2024-11-28 08:55:26 [DEBUG] clck_gen.py:102 IND CLOCK 14280
2024-11-28 08:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 14382
2024-11-28 08:55:27 [DEBUG] clck_gen.py:102 IND CLOCK 14484
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:55:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:55:28 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:55:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:55:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 14586
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:55:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:55:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:55:28 [DEBUG] clck_gen.py:102 IND CLOCK 14688
2024-11-28 08:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 14790
2024-11-28 08:55:29 [DEBUG] clck_gen.py:102 IND CLOCK 14892
2024-11-28 08:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 14994
2024-11-28 08:55:30 [DEBUG] clck_gen.py:102 IND CLOCK 15096
2024-11-28 08:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 15198
2024-11-28 08:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 15300
2024-11-28 08:55:31 [DEBUG] clck_gen.py:102 IND CLOCK 15402
2024-11-28 08:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 15504
2024-11-28 08:55:32 [DEBUG] clck_gen.py:102 IND CLOCK 15606
2024-11-28 08:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 15708
2024-11-28 08:55:33 [DEBUG] clck_gen.py:102 IND CLOCK 15810
2024-11-28 08:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 15912
2024-11-28 08:55:34 [DEBUG] clck_gen.py:102 IND CLOCK 16014
2024-11-28 08:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 16116
2024-11-28 08:55:35 [DEBUG] clck_gen.py:102 IND CLOCK 16218
2024-11-28 08:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 16320
2024-11-28 08:55:36 [DEBUG] clck_gen.py:102 IND CLOCK 16422
2024-11-28 08:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 16524
2024-11-28 08:55:37 [DEBUG] clck_gen.py:102 IND CLOCK 16626
2024-11-28 08:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 16728
2024-11-28 08:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 16830
2024-11-28 08:55:38 [DEBUG] clck_gen.py:102 IND CLOCK 16932
2024-11-28 08:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 17034
2024-11-28 08:55:39 [DEBUG] clck_gen.py:102 IND CLOCK 17136
2024-11-28 08:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 17238
2024-11-28 08:55:40 [DEBUG] clck_gen.py:102 IND CLOCK 17340
2024-11-28 08:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 17442
2024-11-28 08:55:41 [DEBUG] clck_gen.py:102 IND CLOCK 17544
2024-11-28 08:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 17646
2024-11-28 08:55:42 [DEBUG] clck_gen.py:102 IND CLOCK 17748
2024-11-28 08:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 17850
2024-11-28 08:55:43 [DEBUG] clck_gen.py:102 IND CLOCK 17952
2024-11-28 08:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 18054
2024-11-28 08:55:44 [DEBUG] clck_gen.py:102 IND CLOCK 18156
2024-11-28 08:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 18258
2024-11-28 08:55:45 [DEBUG] clck_gen.py:102 IND CLOCK 18360
2024-11-28 08:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 18462
2024-11-28 08:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 18564
2024-11-28 08:55:46 [DEBUG] clck_gen.py:102 IND CLOCK 18666
2024-11-28 08:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 18768
2024-11-28 08:55:47 [DEBUG] clck_gen.py:102 IND CLOCK 18870
2024-11-28 08:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 18972
2024-11-28 08:55:48 [DEBUG] clck_gen.py:102 IND CLOCK 19074
2024-11-28 08:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 19176
2024-11-28 08:55:49 [DEBUG] clck_gen.py:102 IND CLOCK 19278
2024-11-28 08:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 19380
2024-11-28 08:55:50 [DEBUG] clck_gen.py:102 IND CLOCK 19482
2024-11-28 08:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 19584
2024-11-28 08:55:51 [DEBUG] clck_gen.py:102 IND CLOCK 19686
2024-11-28 08:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 19788
2024-11-28 08:55:52 [DEBUG] clck_gen.py:102 IND CLOCK 19890
2024-11-28 08:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 19992
2024-11-28 08:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 20094
2024-11-28 08:55:53 [DEBUG] clck_gen.py:102 IND CLOCK 20196
2024-11-28 08:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 20298
2024-11-28 08:55:54 [DEBUG] clck_gen.py:102 IND CLOCK 20400
2024-11-28 08:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 20502
2024-11-28 08:55:55 [DEBUG] clck_gen.py:102 IND CLOCK 20604
2024-11-28 08:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 20706
2024-11-28 08:55:56 [DEBUG] clck_gen.py:102 IND CLOCK 20808
2024-11-28 08:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 20910
2024-11-28 08:55:57 [DEBUG] clck_gen.py:102 IND CLOCK 21012
2024-11-28 08:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 21114
2024-11-28 08:55:58 [DEBUG] clck_gen.py:102 IND CLOCK 21216
2024-11-28 08:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 21318
2024-11-28 08:55:59 [DEBUG] clck_gen.py:102 IND CLOCK 21420
2024-11-28 08:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 21522
2024-11-28 08:56:00 [DEBUG] clck_gen.py:102 IND CLOCK 21624
2024-11-28 08:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 21726
2024-11-28 08:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 21828
2024-11-28 08:56:01 [DEBUG] clck_gen.py:102 IND CLOCK 21930
2024-11-28 08:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 22032
2024-11-28 08:56:02 [DEBUG] clck_gen.py:102 IND CLOCK 22134
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 22236
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:03 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:03 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:56:03 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:03 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:03 [DEBUG] clck_gen.py:102 IND CLOCK 22338
2024-11-28 08:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 22440
2024-11-28 08:56:04 [DEBUG] clck_gen.py:102 IND CLOCK 22542
2024-11-28 08:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 22644
2024-11-28 08:56:05 [DEBUG] clck_gen.py:102 IND CLOCK 22746
2024-11-28 08:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 22848
2024-11-28 08:56:06 [DEBUG] clck_gen.py:102 IND CLOCK 22950
2024-11-28 08:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 23052
2024-11-28 08:56:07 [DEBUG] clck_gen.py:102 IND CLOCK 23154
2024-11-28 08:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 23256
2024-11-28 08:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 23358
2024-11-28 08:56:08 [DEBUG] clck_gen.py:102 IND CLOCK 23460
2024-11-28 08:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 23562
2024-11-28 08:56:09 [DEBUG] clck_gen.py:102 IND CLOCK 23664
2024-11-28 08:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 23766
2024-11-28 08:56:10 [DEBUG] clck_gen.py:102 IND CLOCK 23868
2024-11-28 08:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 23970
2024-11-28 08:56:11 [DEBUG] clck_gen.py:102 IND CLOCK 24072
2024-11-28 08:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 24174
2024-11-28 08:56:12 [DEBUG] clck_gen.py:102 IND CLOCK 24276
2024-11-28 08:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 24378
2024-11-28 08:56:13 [DEBUG] clck_gen.py:102 IND CLOCK 24480
2024-11-28 08:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 24582
2024-11-28 08:56:14 [DEBUG] clck_gen.py:102 IND CLOCK 24684
2024-11-28 08:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 24786
2024-11-28 08:56:15 [DEBUG] clck_gen.py:102 IND CLOCK 24888
2024-11-28 08:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 24990
2024-11-28 08:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 25092
2024-11-28 08:56:16 [DEBUG] clck_gen.py:102 IND CLOCK 25194
2024-11-28 08:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 25296
2024-11-28 08:56:17 [DEBUG] clck_gen.py:102 IND CLOCK 25398
2024-11-28 08:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 25500
2024-11-28 08:56:18 [DEBUG] clck_gen.py:102 IND CLOCK 25602
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:19 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:56:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:24 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:29 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:29 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:29 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:29 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:56:29 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:56:29 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:56:29 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:56:29 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:56:29 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:29 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:29 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:56:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:30 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:56:31 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:31 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:56:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:32 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:33 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:33 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:56:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:56:34 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:56:35 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:56:36 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:36 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:36 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:36 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:37 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:56:37 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:56:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:56:37 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:56:38 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:38 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:38 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:56:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:56:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:56:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:56:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:56:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:43 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:43 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:56:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:44 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:56:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:45 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:56:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:46 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:56:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:47 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:56:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:56:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:56:48 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:56:49 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:56:50 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:56:51 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:56:52 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:56:53 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:56:54 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:56:55 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:56:56 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:56:57 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:56:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:56:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:56:58 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:56:58 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:56:59 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:57:00 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:57:01 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:57:02 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:57:03 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:57:04 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:57:05 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:57:06 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:57:07 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:57:08 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:57:09 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:57:10 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:57:11 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:57:12 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:13 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:13 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:57:13 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:13 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:13 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:57:14 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:57:15 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:57:16 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:57:17 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:57:18 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:57:19 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:57:20 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:57:21 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:57:22 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 8670
2024-11-28 08:57:23 [DEBUG] clck_gen.py:102 IND CLOCK 8772
2024-11-28 08:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 8874
2024-11-28 08:57:24 [DEBUG] clck_gen.py:102 IND CLOCK 8976
2024-11-28 08:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 9078
2024-11-28 08:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 9180
2024-11-28 08:57:25 [DEBUG] clck_gen.py:102 IND CLOCK 9282
2024-11-28 08:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 9384
2024-11-28 08:57:26 [DEBUG] clck_gen.py:102 IND CLOCK 9486
2024-11-28 08:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 9588
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:27 [DEBUG] clck_gen.py:102 IND CLOCK 9690
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:57:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:57:27 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 9792
2024-11-28 08:57:28 [DEBUG] clck_gen.py:102 IND CLOCK 9894
2024-11-28 08:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 9996
2024-11-28 08:57:29 [DEBUG] clck_gen.py:102 IND CLOCK 10098
2024-11-28 08:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 10200
2024-11-28 08:57:30 [DEBUG] clck_gen.py:102 IND CLOCK 10302
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:31 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:57:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:57:31 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:57:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:57:36 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:57:36 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:57:36 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:57:36 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:57:36 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:57:36 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:57:36 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:57:36 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:57:41 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:57:41 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:57:41 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:57:41 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:57:41 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:57:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:57:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:57:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:57:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:57:41 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:41 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:42 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:57:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:57:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:57:43 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:44 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:44 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:57:44 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:57:45 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:45 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:57:45 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:57:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:57:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:57:46 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:57:47 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:57:48 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:57:49 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:57:50 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:57:51 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:57:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:57:52 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:57:52 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:57:52 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:57:53 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:57:54 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:57:55 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:57:56 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:57:57 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:57:58 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:57:59 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:58:00 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:58:01 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:02 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:02 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:02 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:02 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:02 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:58:03 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 08:58:04 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 08:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 08:58:05 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 08:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 08:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 08:58:06 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 08:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 08:58:07 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 08:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 08:58:08 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 08:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:09 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:09 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:09 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:09 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:09 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 08:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 08:58:10 [DEBUG] clck_gen.py:102 IND CLOCK 6426
2024-11-28 08:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 6528
2024-11-28 08:58:11 [DEBUG] clck_gen.py:102 IND CLOCK 6630
2024-11-28 08:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 6732
2024-11-28 08:58:12 [DEBUG] clck_gen.py:102 IND CLOCK 6834
2024-11-28 08:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 6936
2024-11-28 08:58:13 [DEBUG] clck_gen.py:102 IND CLOCK 7038
2024-11-28 08:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 7140
2024-11-28 08:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 7242
2024-11-28 08:58:14 [DEBUG] clck_gen.py:102 IND CLOCK 7344
2024-11-28 08:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 7446
2024-11-28 08:58:15 [DEBUG] clck_gen.py:102 IND CLOCK 7548
2024-11-28 08:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 7650
2024-11-28 08:58:16 [DEBUG] clck_gen.py:102 IND CLOCK 7752
2024-11-28 08:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 7854
2024-11-28 08:58:17 [DEBUG] clck_gen.py:102 IND CLOCK 7956
2024-11-28 08:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 8058
2024-11-28 08:58:18 [DEBUG] clck_gen.py:102 IND CLOCK 8160
2024-11-28 08:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 8262
2024-11-28 08:58:19 [DEBUG] clck_gen.py:102 IND CLOCK 8364
2024-11-28 08:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 8466
2024-11-28 08:58:20 [DEBUG] clck_gen.py:102 IND CLOCK 8568
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:58:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:58:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:58:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:58:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:26 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:26 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:27 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:27 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:27 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:27 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:27 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:28 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:58:28 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:58:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:58:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:58:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:32 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:32 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=1389 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:58:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:58:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:58:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:58:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:37 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:37 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:58:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:38 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:58:39 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:39 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:58:39 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:58:40 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:40 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:40 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:40 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:58:41 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:58:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:58:42 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:58:43 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:44 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:44 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:44 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:44 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:44 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:58:45 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:58:46 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:58:47 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:58:48 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:58:49 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:58:50 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:58:51 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:58:52 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:52 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:58:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:58:57 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:58:57 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:58:57 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:58:57 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:57 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:57 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:58:58 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:58:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:58:59 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:58:59 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:58:59 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:00 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:00 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:59:00 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:00 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:00 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:59:01 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:01 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:59:01 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:59:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:59:02 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:59:03 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:59:04 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:59:05 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:59:06 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:59:07 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:59:08 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:59:09 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:59:10 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:59:11 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:59:12 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 08:59:13 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 08:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 08:59:14 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 08:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 08:59:15 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 08:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 08:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 08:59:16 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 08:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 08:59:17 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 08:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 08:59:18 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 08:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 08:59:19 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:20 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:20 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:59:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:59:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:20 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=4955 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:59:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:59:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:59:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:59:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:59:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:59:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:59:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:59:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:59:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:59:26 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:59:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:59:27 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:28 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:28 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:59:28 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:28 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:28 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:59:29 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:29 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:59:29 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:59:30 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:30 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:59:30 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:59:31 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:59:32 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:33 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:33 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:59:34 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:59:35 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:59:36 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:59:37 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:59:38 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 08:59:39 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:39 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:39 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:59:39 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:39 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 08:59:40 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:40 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:40 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:59:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:59:40 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:59:45 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:59:45 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:59:45 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:59:45 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 08:59:45 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 08:59:45 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 08:59:45 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 08:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 08:59:46 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 08:59:46 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:46 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:46 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:46 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:46 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:46 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 08:59:47 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 08:59:47 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:47 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:48 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:48 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:59:48 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 08:59:48 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 08:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 08:59:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:49 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 08:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:50 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:50 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:50 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:50 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:50 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 08:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 08:59:51 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 08:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 08:59:52 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 08:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 08:59:53 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 08:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 08:59:54 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 08:59:55 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 08:59:55 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.74.22:6700) Recv SETFH cmd
2024-11-28 08:59:55 [INFO] transceiver.py:201 (MS@172.18.74.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:55 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 08:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 08:59:55 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 08:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 08:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 08:59:56 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 08:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 08:59:57 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 08:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 08:59:58 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 08:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 08:59:59 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 09:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 09:00:00 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 09:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 09:00:01 [DEBUG] clck_gen.py:102 IND CLOCK 3468
2024-11-28 09:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 3570
2024-11-28 09:00:02 [DEBUG] clck_gen.py:102 IND CLOCK 3672
2024-11-28 09:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 3774
2024-11-28 09:00:03 [DEBUG] clck_gen.py:102 IND CLOCK 3876
2024-11-28 09:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 3978
2024-11-28 09:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4080
2024-11-28 09:00:04 [DEBUG] clck_gen.py:102 IND CLOCK 4182
2024-11-28 09:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 4284
2024-11-28 09:00:05 [DEBUG] clck_gen.py:102 IND CLOCK 4386
2024-11-28 09:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 4488
2024-11-28 09:00:06 [DEBUG] clck_gen.py:102 IND CLOCK 4590
2024-11-28 09:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 4692
2024-11-28 09:00:07 [DEBUG] clck_gen.py:102 IND CLOCK 4794
2024-11-28 09:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 4896
2024-11-28 09:00:08 [DEBUG] clck_gen.py:102 IND CLOCK 4998
2024-11-28 09:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 5100
2024-11-28 09:00:09 [DEBUG] clck_gen.py:102 IND CLOCK 5202
2024-11-28 09:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 5304
2024-11-28 09:00:10 [DEBUG] clck_gen.py:102 IND CLOCK 5406
2024-11-28 09:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 5508
2024-11-28 09:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 5610
2024-11-28 09:00:11 [DEBUG] clck_gen.py:102 IND CLOCK 5712
2024-11-28 09:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 5814
2024-11-28 09:00:12 [DEBUG] clck_gen.py:102 IND CLOCK 5916
2024-11-28 09:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6018
2024-11-28 09:00:13 [DEBUG] clck_gen.py:102 IND CLOCK 6120
2024-11-28 09:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 6222
2024-11-28 09:00:14 [DEBUG] clck_gen.py:102 IND CLOCK 6324
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:00:15 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:00:15 [INFO] transceiver.py:205 (MS@172.18.74.22:6700) Frequency hopping disabled
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:15 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=6382 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:21 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:21 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:21 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:21 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:26 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:26 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:26 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:26 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:26 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:26 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:26 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:27 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:27 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:27 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:27 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:27 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:28 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:28 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:28 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:33 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:33 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:33 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:33 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:33 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:33 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:33 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:34 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:34 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:34 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:34 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:35 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:35 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:35 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:40 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:40 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:40 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:40 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:40 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:40 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:40 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:41 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:41 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:41 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:41 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:42 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:42 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:42 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:47 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:47 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:47 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:47 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:47 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:47 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:47 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:48 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:48 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:48 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:48 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:49 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:49 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:49 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:49 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:54 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:54 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:54 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:54 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:00:54 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:00:54 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:00:54 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:00:55 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:00:55 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:55 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:00:56 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:00:56 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:00:56 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:00:56 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=420 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:01 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:01 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:01 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:01 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:01 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:01 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:01 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:02 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:02 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:02 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:03 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:08 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:08 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:08 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:08 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:08 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:08 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:08 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:09 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:09 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:09 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:09 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:09 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:09 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:09 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:14 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:14 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:14 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:14 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:14 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:14 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:14 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:14 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:14 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:14 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:15 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:15 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:15 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:20 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:20 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:20 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:20 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:20 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:20 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:20 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:20 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:20 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:20 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:20 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:25 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:25 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:25 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:25 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:25 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:25 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:25 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:26 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:26 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:26 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:26 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:26 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:26 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:31 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:31 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:31 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:31 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:31 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:31 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:31 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:32 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:32 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:32 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:32 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:32 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:32 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:32 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=147 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:37 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:37 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:37 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:37 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:37 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:37 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:37 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:37 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:37 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:37 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:37 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:38 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=165 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:43 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:43 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:43 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:48 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:49 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:49 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:49 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:01:49 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:01:49 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:01:49 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:49 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:01:50 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:01:50 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:50 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 09:01:51 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 09:01:51 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:51 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 09:01:52 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:01:52 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:52 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:52 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:52 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:57 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:57 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:57 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:57 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:01:57 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:01:57 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:01:57 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:01:58 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:01:58 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:58 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:58 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:01:58 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:01:58 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:01:58 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:01:58 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:03 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:03 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:03 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:03 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:04 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:04 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:04 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:04 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:04 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:02:04 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:02:04 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:04 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:04 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:04 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:04 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:02:05 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:05 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:02:05 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:02:06 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:06 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 09:02:06 [DEBUG] clck_gen.py:102 IND CLOCK 612
2024-11-28 09:02:07 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:07 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 714
2024-11-28 09:02:07 [DEBUG] clck_gen.py:102 IND CLOCK 816
2024-11-28 09:02:08 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:08 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 918
2024-11-28 09:02:08 [DEBUG] clck_gen.py:102 IND CLOCK 1020
2024-11-28 09:02:09 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:09 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1122
2024-11-28 09:02:09 [DEBUG] clck_gen.py:102 IND CLOCK 1224
2024-11-28 09:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 1326
2024-11-28 09:02:10 [DEBUG] clck_gen.py:102 IND CLOCK 1428
2024-11-28 09:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 1530
2024-11-28 09:02:11 [DEBUG] clck_gen.py:102 IND CLOCK 1632
2024-11-28 09:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 1734
2024-11-28 09:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 1836
2024-11-28 09:02:12 [DEBUG] clck_gen.py:102 IND CLOCK 1938
2024-11-28 09:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 2040
2024-11-28 09:02:13 [DEBUG] clck_gen.py:102 IND CLOCK 2142
2024-11-28 09:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 2244
2024-11-28 09:02:14 [DEBUG] clck_gen.py:102 IND CLOCK 2346
2024-11-28 09:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 2448
2024-11-28 09:02:15 [DEBUG] clck_gen.py:102 IND CLOCK 2550
2024-11-28 09:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 2652
2024-11-28 09:02:16 [DEBUG] clck_gen.py:102 IND CLOCK 2754
2024-11-28 09:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 2856
2024-11-28 09:02:17 [DEBUG] clck_gen.py:102 IND CLOCK 2958
2024-11-28 09:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 3060
2024-11-28 09:02:18 [DEBUG] clck_gen.py:102 IND CLOCK 3162
2024-11-28 09:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 3264
2024-11-28 09:02:19 [DEBUG] clck_gen.py:102 IND CLOCK 3366
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:19 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:19 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:19 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:19 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:19 [WARNING] transceiver.py:250 (BTS@172.18.74.20:5700) RX TRXD message (ver=1 fn=3441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:24 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:24 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:24 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:24 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:24 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:24 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:24 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:02:25 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:02:25 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:02:25 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:02:25 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:25 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:25 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:25 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:30 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:30 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:30 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:30 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:30 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:30 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:30 [DEBUG] clck_gen.py:102 IND CLOCK 0
2024-11-28 09:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 102
2024-11-28 09:02:31 [DEBUG] fake_trx.py:272 (BTS@172.18.74.20:5700) Recv FAKE_TOA cmd
2024-11-28 09:02:31 [DEBUG] fake_trx.py:291 (BTS@172.18.74.20:5700) Recv FAKE_RSSI cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:31 [DEBUG] fake_trx.py:316 (BTS@172.18.74.20:5700) Recv FAKE_CI cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:31 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:31 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD HANDOVER
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:31 [DEBUG] clck_gen.py:102 IND CLOCK 204
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:31 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 306
2024-11-28 09:02:32 [DEBUG] clck_gen.py:102 IND CLOCK 408
2024-11-28 09:02:32 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:32 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:33 [DEBUG] clck_gen.py:102 IND CLOCK 510
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD ECHO
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.74.22:6700) Ignore CMD SETSLOT
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.74.22:6700) Recv RXTUNE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.74.22:6700) Recv TXTUNE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.74.22:6700) Recv POWERON CMD
2024-11-28 09:02:33 [INFO] ctrl_if_trx.py:109 (MS@172.18.74.22:6700) Starting transceiver...
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD NOHANDOVER
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.74.22:6700) Recv POWEROFF cmd
2024-11-28 09:02:33 [INFO] ctrl_if_trx.py:117 (MS@172.18.74.22:6700) Stopping transceiver...
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.74.20:5700) Recv SETPOWER cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.74.20:5700/1) Recv SETPOWER cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.74.20:5700/2) Recv SETPOWER cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.74.20:5700/3) Recv SETPOWER cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:33 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:33 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:33 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:38 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:38 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:38 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:38 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:38 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:38 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:38 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:38 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:43 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:43 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:43 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:43 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:43 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:43 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:43 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:43 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:48 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.74.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.74.20:5700) Recv SETFORMAT cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:201 (BTS@172.18.74.20:5700) TRXD header version 1 -> 1
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.74.20:5700/1) Recv RXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.74.20:5700/1) Recv TXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:48 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.74.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.74.20:5700/1) Recv NOMTXPOWER cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.74.20:5700/1) Recv SETFORMAT cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.74.20:5700/1) TRXD header version 1 -> 1
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.74.20:5700/2) Recv RXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.74.20:5700/2) Recv TXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:48 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.74.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.74.20:5700/2) Recv NOMTXPOWER cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.74.20:5700/2) Recv SETFORMAT cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.74.20:5700/2) TRXD header version 1 -> 1
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.74.20:5700/3) Recv RXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.74.20:5700/3) Recv TXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:48 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.74.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.74.20:5700/3) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.74.20:5700/3) Recv NOMTXPOWER cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.74.20:5700/3) Recv SETFORMAT cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.74.20:5700/3) TRXD header version 1 -> 1
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.74.20:5700) Recv RXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETTSC
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETTSC
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETTSC
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.74.20:5700) Recv TXTUNE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETRXGAIN
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETTSC
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETRXGAIN
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETRXGAIN
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.74.20:5700) Recv NOMTXPOWER cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.74.20:5700) Recv POWERON CMD
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:109 (BTS@172.18.74.20:5700) Starting transceiver...
2024-11-28 09:02:48 [INFO] transceiver.py:236 Starting clock generator
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETRXGAIN
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.74.20:5700/1) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.74.20:5700/1) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.74.20:5700/2) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.74.20:5700) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.74.20:5700) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.74.20:5700/2) Recv RFMUTE cmd
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.74.20:5700) Recv POWEROFF cmd
2024-11-28 09:02:48 [INFO] ctrl_if_trx.py:117 (BTS@172.18.74.20:5700) Stopping transceiver...
2024-11-28 09:02:48 [INFO] transceiver.py:239 Stopping clock generator
2024-11-28 09:02:48 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.74.20:5700/3) Ignore CMD SETSLOT